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    SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING
    1.
    发明申请
    SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING 有权

    公开(公告)号：US20250054818A1

    公开(公告)日：2025-02-13

    申请号：US18930628

    申请日：2024-10-29

    Applicant: Sandisk Technologies, Inc.

    Inventor： Akira Ogawa ,  Takashi Murai

    IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

    Abstract: An apparatus includes a semiconductor wafer including a first die and a second die, each including, a selector circuit including a first input terminal coupled to a first die bond pad, a second input terminal, and an output terminal, the selector circuit configured to selectively couple the first input terminal and the second input terminal to the output terminal, a conductor selectively configured to couple the second input terminal to either a first power supply or a second power supply, and an address determined based on a signal value at the output terminal of the selector circuit.

    SOLID-STATE DRIVE SECURE DATA WIPING FOR REUSE AND RECYCLING
    2.
    发明申请
    SOLID-STATE DRIVE SECURE DATA WIPING FOR REUSE AND RECYCLING 有权

    公开(公告)号：US20250004660A1

    公开(公告)日：2025-01-02

    申请号：US18230145

    申请日：2023-08-03

    Applicant: Sandisk Technologies, Inc.

    Inventor： Daniel J. Linnen ,  Ramanathan Muthiah ,  Preston Thomson ,  Kirubakaran Periyannan ,  Niles Nian Yang ,  Inez Hua ,  Judah Gamliel Hahn

    IPC: G06F3/06

    Abstract: A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.

    CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY
    3.
    发明申请
    CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY 有权

    公开(公告)号：US20240395328A1

    公开(公告)日：2024-11-28

    申请号：US18790609

    申请日：2024-07-31

    Applicant: Sandisk Technologies, Inc.

    Inventor： Abhijith Prakash ,  Anubhav Khandelwal

    IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

    Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

    Systems and methods for improving find last good page processing in memory devices
    4.
    发明授权
    Systems and methods for improving find last good page processing in memory devices 有权

    公开(公告)号：US12124704B2

    公开(公告)日：2024-10-22

    申请号：US18356693

    申请日：2023-07-21

    Applicant: Western Digital Technologies, Inc.

    Inventor： Asaf Gueta ,  Arie Star ,  Omer Fainzilber ,  Eran Sharon

    IPC: G06F3/06

    CPC classification number: G06F3/0614 ,  G06F3/064 ,  G06F3/0679

    Abstract: A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.

    DRAM-less SSD with HMB cache management
    5.
    发明授权
    DRAM-less SSD with HMB cache management 有权

    公开(公告)号：US12118242B2

    公开(公告)日：2024-10-15

    申请号：US17657456

    申请日：2022-03-31

    Applicant: Western Digital Technologies, Inc.

    Inventor： Judah Gamliel Hahn ,  Shay Benisty ,  Ariel Navon

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679

    Abstract: The present disclosure generally relates to host memory buffer (HMB) cache management in DRAM-less SSDs. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas that have occurred since either the last copying to an HMB cache in the memory device or any delta that have occurred since the link became inactive. The HMB cache mirrors the HMB. In so doing, the data of the HMB is available to the data storage device not only when the link is active, but also when the link is not active.

    Self-aligning heat fins for thermal management
    7.
    发明授权
    Self-aligning heat fins for thermal management 有权

    公开(公告)号：US12108577B2

    公开(公告)日：2024-10-01

    申请号：US17743184

    申请日：2022-05-12

    Applicant: Western Digital Technologies, Inc.

    Inventor： Uthayarajan A/L Rasalingam ,  Vijay A/L Mohanarao

    IPC: H05K7/20

    CPC classification number: H05K7/20509 ,  H05K7/20 ,  H05K7/20009 ,  H05K7/20418 ,  H05K7/205

    Abstract: A thermal dissipation device for use with electronic assemblies or devices and that includes a heat conductive plate configured to thermally couple to one or more packaged components on a first side of the heat conductive plate. The thermal dissipation device further includes a heat conductive post coupled to a second side of the heat conductive plate. The heat conductive post includes a fin member rotatably coupled to the heat conductive post, which is configured to rotate about an axis of the heat conductive post to maximize both a flow of air across the fin member and thermal dissipation of heat from the heat conductive plate into the atmosphere.

    Parallel fragmented SGL fetching for hiding host turnaround time
    8.
    发明授权
    Parallel fragmented SGL fetching for hiding host turnaround time 有权

    公开(公告)号：US12105990B2

    公开(公告)日：2024-10-01

    申请号：US17943767

    申请日：2022-09-13

    Applicant: Western Digital Technologies, Inc.

    Inventor： Shay Benisty

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0652 ,  G06F3/0673

    Abstract: The present disclosure generally relates to reducing latency when fetching Scatter Gather Lists (SGL). Rather than fetching the required SGLs sequentially regardless of what SGL descriptor is needed, the data storage device fetches all of the last entries of each SGL segment in ahead of time after receiving the command, but before the read data is available. The data storage device will still fetch the previous entries in the segment. Once the last entries are fetched, the last entries are stored in a table where the earlier descriptors of each segment are stored as the segments are fetched. In so doing, parallel fetching allows the data storage device to fetch SGL descriptors as needed and reduces the latency.

    Systems and methods of compensating degradation in analog compute-in-memory (ACIM) modules
    9.
    发明授权
    Systems and methods of compensating degradation in analog compute-in-memory (ACIM) modules 有权

    公开(公告)号：US12086461B2

    公开(公告)日：2024-09-10

    申请号：US17347472

    申请日：2021-06-14

    Applicant: Western Digital Technologies, Inc.

    Inventor： Chao Sun ,  Tung Thanh Hoang ,  Dejan Vucinic

    IPC: G06F3/06 ,  G06N20/00

    CPC classification number: G06F3/0659 ,  G06F3/0616 ,  G06F3/0673 ,  G06N20/00

    Abstract: Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply analog weights to input data using multiply-accumulate operations to generate an output. The device further comprises a digital weight storage unit configured to store digital weight references, wherein a digital weight reference corresponds to an analog weight of the analog weights. The device also comprises a device controller configured to program the analog weights to the CIM module, cause the CIM module to process the input data, and reprogram one or more analog weights that are degraded. The digital weight references in the digital weight storage unit are populated with values from a host processing device. Degraded analog weights in the CIM module are reprogrammed based on the corresponding digital weight references from the digital weight storage unit without reference to the host processing device.

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