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公开(公告)号：US20240422938A1
公开(公告)日：2024-12-19
申请号：US18449483
申请日：2023-08-14
Applicant: Western Digital Technologies, Inc.
Inventor： Uthayarajan A/L Rasalingam , Niladri Dey
Abstract: A data storage device includes TE elements thermally connected between IC chips thereof and a lid assembly. An electronic controller of the data storage device is configured to receive voltages generated by the TE elements in response to the heat generated in the IC chips and is further configured to use the voltages to provide electrical power to an electrical fan of the lid assembly. The fan generates an airflow for keeping the lid assembly at approximately ambient temperature, thereby facilitating heat removal from the IC chips by way of the TE elements.
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公开(公告)号：US20240414851A1
公开(公告)日：2024-12-12
申请号：US18360094
申请日：2023-07-27
Applicant: Western Digital Technologies, Inc.
Inventor： Uthayarajan A/L Rasalingam , Choo Par Tan , Mathavan Valu
Abstract: A printed circuit board (PCB) includes an identified temperature profiling location. The identified temperature profiling location may be a connection pad from a grid of connection pads on the PCB. The connection pad may be located near a center of the grid of connection pads. The connection pad may be coupled to a no-connect pin of an electronic component that is surface mounted to the PCB. Traces extend from the connection pad to test pads provided near a perimeter of the grid of connection pads. A temperature measurement device may be coupled to the test pads, which enables the temperature measurement device to capture accurate temperature readings underneath the electronic component during a reflow profiling process.
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公开(公告)号：US20230156921A1
公开(公告)日：2023-05-18
申请号：US17527687
申请日：2021-11-16
Applicant: Western Digital Technologies, Inc.
Inventor： Uthayarajan A/L Rasalingam , Alexander Beh
CPC classification number: H05K1/181 , H01L24/16 , H01L2224/10135 , H01L2224/16225 , H05K2201/09827 , H05K2201/10159 , H01L2924/1438
Abstract: A data storage device includes a substrate and one or more grid array integrated circuit packages. The grid array integrated circuit package includes at least one self-alignment pin having a tapered shape. The substrate includes one or more connection pads to receive the grid array integrated circuit packages. The connection pads include at least one self-alignment receptacle that receives the self-alignment pins such that the grid array integrated circuit packages maintain an alignment with an associated connection pad of the substrate.
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公开(公告)号：US12237275B2
公开(公告)日：2025-02-25
申请号：US17675951
申请日：2022-02-18
Applicant: Western Digital Technologies, Inc.
Inventor： Uthayarajan A/L Rasalingam , Janice Jia Min Ling
IPC: H01L21/00 , H01L23/00 , H01L23/31 , H01L23/367 , H01L23/48 , H01L23/49 , H01L23/528 , H01L25/065
Abstract: A semiconductor package includes a substrate having a first surface, and a second surface opposite the first surface. The substrate includes a connection region having a first array of contact pads, and a peripheral region surrounding the connection region and having additional contact pads. A semiconductor die having an array of electrical contacts and thermal contacts, is connected to the first array of contact pads and to the additional contact pads. A plate is coupled to a top surface of the semiconductor die and there is at least one pin projecting from the plate toward the first substrate. The pin is disposed within a channel that extends between the plate and the additional contact. The plate, channel and pin improve the heat dissipation capabilities of the semiconductor device package.
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公开(公告)号：US20230369791A1
公开(公告)日：2023-11-16
申请号：US17740836
申请日：2022-05-10
Applicant: Western Digital Technologies, Inc.
Inventor： Uthayarajan A/L Rasalingam
Abstract: A connector for communicatively coupling an electronic device to a host device is provided. The connector includes a mating side and a termination side for surface mounting the connector to the electronic device. The mating side includes a first contact and a second contact. The termination side includes a printed circuit board and a grid of connection points provided on a bottom surface of the printed circuit board. The first contact is communicatively coupled to a first connection point in the grid of connection points and the second contact is communicatively coupled to a second connection point in the grid of connection points.
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Patent Agency Ranking
公开(公告)号：US20220271456A1
公开(公告)日：2022-08-25
申请号：US17180067
申请日：2021-02-19
Applicant: Western Digital Technologies, Inc.
Inventor： Uthayarajan A/L Rasalingam , Go Beng Siong
Abstract: A data storage device including a first printed circuit board (PCB) and a second PCB. The first PCB includes a controller, an interface configured to interface with a host device, and a first connector. The second PCB includes a non-volatile memory and a second connector. The second connector is configured to couple to the first connector to establish a communication connection between the controller and the non-volatile memory.
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公开(公告)号：US12108577B2
公开(公告)日：2024-10-01
申请号：US17743184
申请日：2022-05-12
Applicant: Western Digital Technologies, Inc.
Inventor： Uthayarajan A/L Rasalingam , Vijay A/L Mohanarao
IPC: H05K7/20
CPC classification number: H05K7/20509 , H05K7/20 , H05K7/20009 , H05K7/20418 , H05K7/205
Abstract: A thermal dissipation device for use with electronic assemblies or devices and that includes a heat conductive plate configured to thermally couple to one or more packaged components on a first side of the heat conductive plate. The thermal dissipation device further includes a heat conductive post coupled to a second side of the heat conductive plate. The heat conductive post includes a fin member rotatably coupled to the heat conductive post, which is configured to rotate about an axis of the heat conductive post to maximize both a flow of air across the fin member and thermal dissipation of heat from the heat conductive plate into the atmosphere.
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公开(公告)号：US20240324109A1
公开(公告)日：2024-09-26
申请号：US18357379
申请日：2023-07-24
Applicant: Western Digital Technologies, Inc.
CPC classification number: H05K3/3436 , H05K1/181 , H05K2201/09136 , H05K2201/10734 , H05K2203/041 , H05K2203/0557
Abstract: A grid of connection points or surface mount features electrically and/or communicatively couples a first computing component to a second computing component. The grid of connection points include a first connection point type having a first structure and a second connection point type having a second structure. In an example, the first connection point type is a solder ball that is associated with a single signal pin and the second connection point type is a solder bar that is associated with multiple signal pins. One or more of the second connection point types are positioned at and/or around a perimeter of the first computing component, which reduces strain, stress and/or other mechanical forces on the first connection point types and/or on the first computing component and/or the second computing component.
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公开(公告)号：US20230343690A1
公开(公告)日：2023-10-26
申请号：US17724617
申请日：2022-04-20
Applicant: Western Digital Technologies, Inc.
IPC: H01L23/498 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49838 , H01L24/48 , H01L23/3128 , H01L23/49816 , H01L2224/48227
Abstract: A semiconductor device package includes a substrate having a top and bottom surface and an electrical circuit. There is a semiconductor die electrically connected to the electrical circuit of the substrate. There are N adjacent first electrical contacts and N is an integer greater than 1. The N adjacent first electrical contacts are positioned within a first contact area on the bottom surface of the substrate. There is a second electrical contact that is associated with N independent common signals that are electrically connected at a single second electrical contact. The second electrical contact is positioned within a second contact area on the bottom surface of the substrate that is smaller than the first contact area. The second electrical contact reduces the total area required on the substrate for common signal contacts to allow for additional non-common signal contacts to be included in the semiconductor device package.
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公开(公告)号：US20230268290A1
公开(公告)日：2023-08-24
申请号：US17675951
申请日：2022-02-18
Applicant: Western Digital Technologies, Inc.
Inventor： Uthayarajan A/L Rasalingam , Janice Jia Min Ling
IPC: H01L23/00 , H01L25/065 , H01L23/367 , H01L23/31 , H01L23/48 , H01L23/528 , H01L23/49
CPC classification number: H01L23/562 , H01L25/0657 , H01L23/3677 , H01L23/3128 , H01L23/481 , H01L23/5286 , H01L23/49 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/06586 , H01L2225/06589
Abstract: A semiconductor package includes a substrate having a first surface, and a second surface opposite the first surface. The substrate includes a connection region having a first array of contact pads, and a peripheral region surrounding the connection region and having additional contact pads. A semiconductor die having an array of electrical contacts and thermal contacts, is connected to the first array of contact pads and to the additional contact pads. A plate is coupled to a top surface of the semiconductor die and there is at least one pin projecting from the plate toward the first substrate. The pin is disposed within a channel that extends between the plate and the additional contact. The plate, channel and pin improve the heat dissipation capabilities of the semiconductor device package.
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