公开(公告)号：US5481137A

公开(公告)日：1996-01-02

申请号：US246375

申请日：1994-05-18

Applicant: Shigeru Harada ,  Hisao Masuda ,  Reiji Tamaki

Inventor： Shigeru Harada ,  Hisao Masuda ,  Reiji Tamaki

IPC: H01L23/532 ,  H01L23/48 ,  H01L29/34 ,  H01L29/46 ,  H01L29/62

CPC classification number: H01L23/53219 ,  H01L23/532 ,  H01L2924/0002

Abstract: In a semiconductor device, an impurity diffused layer serving as an active region is formed in a predetermined region of the surface of a semiconductor substrate of silicon, an underlayer insulating film is formed on the semiconductor substrate for the purpose of protecting and stabilizing the surface of the semiconductor substrate, and an interconnection electrically connected to the impurity diffused layer through a contact hole and formed on an Al-Si-Sn alloy, an Al-Si-Sb alloy or alloys having Ti added to the respective alloys, so that occurrence of an alloy pit and a silicon nodule is prevented. In addition, a completed protective film is formed on the interconnection and the underlayer insulating film and an aperture in a bonding pad region is formed in a predetermined region of the completed protective film, so that the interconnection and the bonding pad are electrically connected to each other. The proportion of silicon and other materials in the alloy are controlled to simultaneously avoid alloy pit and silicon nodule defects both at the contact hole and throughout the alloy conductor.

Abstract translation: 在半导体器件中，在硅的半导体衬底的表面的预定区域中形成用作有源区的杂质扩散层，为了保护和稳定表面的目的，在半导体衬底上形成下层绝缘膜 半导体衬底以及通过接触孔与杂质扩散层电连接并且在Al-Si-Sn合金，Al-Si-Sb合金或其合金上添加有Ti的合金形成的互连，从而发生 防止了合金凹坑和硅结节。 此外，在互连和下层绝缘膜上形成完整的保护膜，并且在完成的保护膜的预定区域中形成焊盘区域中的孔，使得互连和焊盘与每个 其他。 控制合金中硅和其他材料的比例，以同时避免接触孔和整个合金导体中的合金凹坑和硅结节缺陷。

公开(公告)号：US5479049A

公开(公告)日：1995-12-26

申请号：US121722

申请日：1993-09-15

Applicant: Tetsuro Aoki ,  Shun-ichi Naka

Inventor： Tetsuro Aoki ,  Shun-ichi Naka

IPC: G02B27/00 ,  H01L23/29 ,  H01L23/31 ,  H01L27/14 ,  H01L31/0216 ,  H01L29/34 ,  H01L31/00

CPC classification number: H01L31/02161 ,  H01L27/14621 ,  H01L27/14627

Abstract: A first transparent protection layer is formed on color filters, and micro lenses are further formed on the first transparent protection layer. Then unevenness due to the micro lenses is flattened by a first transparent resin layer which has water repellency and oil repellency (low surface energy), a high transmittance in visible light range, a high flattening capability in a coating process, and a refractive index lower than the refractive index of the micro lenses. With the above-mentioned arrangement, dust or the like can be difficult to contaminate the surface of the solid state image sensor without loosing the light converging effect of the micro lenses. Even when dust or the like attaches to the surface, it can be easily removed with a cotton swab or the like.

Abstract translation: 第一透明保护层形成在滤色器上，微透镜进一步形成在第一透明保护层上。 然后，通过具有防水性和拒油性（低表面能）的第一透明树脂层，可见光范围的高透射率，涂布过程中的高平坦化能力和折射率较低的第一透明树脂层将由于微透镜引起的凹凸变平 比微透镜的折射率。 利用上述结构，灰尘等可能难以污染固态图像传感器的表面，而不会失去微透镜的聚光效果。 即使当灰尘等附着在表面上时，也可以用棉签等轻易地去除。

公开(公告)号：US5479029A

公开(公告)日：1995-12-26

申请号：US220586

申请日：1994-03-31

Applicant: Satoshi Uchida ,  Hiroaki Takuma ,  Katsuhiko Ikawa

Inventor： Satoshi Uchida ,  Hiroaki Takuma ,  Katsuhiko Ikawa

IPC: H01S3/04 ,  H01L33/64 ,  H01S5/00 ,  H01S5/022 ,  H01S5/024 ,  H01S5/042 ,  H01L31/12 ,  H01L29/161 ,  H01L29/34 ,  H01L33/00

CPC classification number: H01L33/647 ,  H01S5/0224 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01S5/02212 ,  H01S5/02276 ,  H01S5/02469 ,  H01S5/2231

Abstract: The present invention provides a sub-mount type device for emitting light which has high speed response and yet can radiate heat sufficiently. The sub-mount type device for emitting light comprises a heat sink (4), a sub-mount body (62) mounted on the heat sink (4) which comprises an insulating layer (38) with a upper face and a lower face, a upper electrode (42) on the upper face and a lower electrode 44 and 36 on the lower face, the insulating layer having two parts of the insulating layer (38) thickness of which is different, and a chip (30) for emitting light above the thinner part (39) of the insulating layer (38).

Abstract translation: 本发明提供了一种用于发射具有高速响应并且还能够充分散热的光的子安装型装置。 用于发射光的子安装型装置包括散热器（4），安装在散热器（4）上的副安装体（62），其包括具有上表面和下表面的绝缘层（38） 上表面上的上电极（42）和下表面的下电极44和36，所述绝缘层具有厚度不同的绝缘层（38）的两部分，以及用于发光的芯片（30） 在绝缘层（38）的较薄部分（39）之上。

公开(公告)号：US5442198A

公开(公告)日：1995-08-15

申请号：US189498

申请日：1994-01-31

Applicant: Michio Arai ,  Masaaki Ikeda ,  Kazushi Sugiura ,  Nobuo Furukawa ,  Mitsufumi Kodama ,  Yukio Yamauchi ,  Naoya Sakamoto ,  Takeshi Fukada ,  Masaaki Hiroki ,  Ichirou Takayama

Inventor： Michio Arai ,  Masaaki Ikeda ,  Kazushi Sugiura ,  Nobuo Furukawa ,  Mitsufumi Kodama ,  Yukio Yamauchi ,  Naoya Sakamoto ,  Takeshi Fukada ,  Masaaki Hiroki ,  Ichirou Takayama

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  H01L31/105 ,  H04N1/031 ,  H01L21/00 ,  H01L29/161 ,  H01L29/34

CPC classification number: H01L29/66757 ,  H01L21/2022 ,  H01L29/78675 ,  H01L31/1055 ,  H04N1/0313 ,  H04N1/0316 ,  Y10S257/905

Abstract: A MOS-FET transistor is produced on a substrate made of glass which has a non single crystal semiconductor film (2'). The average diameter of a crystal grain in said film is in the range between 0.5 times and 4 times of thickness of said film, and said average diameter is 250 .ANG.-8000 .ANG., and said film thickness is 500 .ANG.-2000 .ANG.. The density of oxygen in the semiconductor film (2') is less than 2.times.10.sup.19 /cm.sup.3. A photo sensor having PIN structure is also produced on the substrate, to provide an image sensor for a facsimile transmitter together with the transistors. Said film (2') is produced by placing amorphous silicon film on the glass substrate through CVD process using disilane gas, and effecting solid phase growth to said amorphous silicon film by heating the substrate together with said film in nitrogen gas atmosphere. The film (2') thus produced is subject to implantation of dopant for providing a transistor. The film thus produced has high mobility which provides high speed operation of a transistor, and low threshold voltage of a transistor.

Abstract translation: 在具有非单晶半导体膜（2'）的由玻璃制成的基板上制造MOS-FET晶体管。 所述膜中的晶粒的平均直径在所述膜的厚度的0.5倍至4倍的范围内，所述平均直径为250安培-8000安培，所述膜厚度为500安培-2000安。 半导体膜（2'）中的氧的密度小于2×10 19 / cm 3。 具有PIN结构的光电传感器也在基板上产生，以便与晶体管一起为传真发送器提供图像传感器。 通过使用乙硅烷气体的CVD法将玻璃基板上的非晶硅膜放置在所述膜（2'）上，通过在氮气气氛中与所述膜一起加热基板，对所述非晶硅膜进行固相生长。 由此产生的薄膜（2'）可以注入用于提供晶体管的掺杂剂。 由此产生的膜具有提供晶体管的高速操作和晶体管的低阈值电压的高迁移率。

公开(公告)号：US5381033A

公开(公告)日：1995-01-10

申请号：US186890

申请日：1994-01-27

Applicant: Kazuo Matsuzaki

Inventor： Kazuo Matsuzaki

IPC: H01L21/762 ,  H01L21/301 ,  H01L21/76 ,  H01L21/763 ,  H01L29/34 ,  H01L27/02 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L21/7624 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76286 ,  Y10S148/012 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S438/928

Abstract: A dielectrics dividing wafer is disclosed in which embedded dielectric films are provided in the interior of the wafer in a predetermined pattern extending laterally parallel to a face surface of the wafer, and partition dielectric films, in the form of vertical walls extending from the face surface and the rear surface of the wafer, to the embedded dielectric films, are provided to define semiconductor areas extending continuously from the face surface of the wafer to the rear surface of the wafer. The semiconductor areas can be used for vertical circuit elements. The partition dielectric films in conjunction with the embedded dielectric films and the face surface of the wafer also define additional planar semiconductor areas that can be used for planar structure circuit elements.

Abstract translation: 公开了一种电介质分隔晶片，其中嵌入的电介质薄膜以预定的图案形式设置在晶片的内部，该图案沿横向平行于晶片的表面横向延伸，并且以垂直壁的形式将电介质薄膜分隔开， 并且提供晶片的后表面到嵌入的介电膜以限定从晶片的表面连续延伸到晶片的后表面的半导体区域。 半导体区域可用于垂直电路元件。 分隔电介质膜与嵌入的电介质膜和晶片的表面结合也限定了可用于平面结构电路元件的另外的平面半导体区域。

公开(公告)号：US5336913A

公开(公告)日：1994-08-09

申请号：US916342

申请日：1992-07-17

Applicant: Takao Kakiuchi ,  Kazuo Sato

Inventor： Takao Kakiuchi ,  Kazuo Sato

IPC: H01L21/8247 ,  G11C11/34 ,  H01L21/336 ,  H01L27/115 ,  H01L29/34 ,  H01L29/68 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/7883 ,  H01L27/115

Abstract: A long-life, electrically writable and erasable non-volatile semiconductor memory device is disclosed. The memory device is fabricated in the following steps. After forming a first gate insulating film on a semiconductor substrate, a window is opened in the first gate insulating film to expose a portion of the surface of the semiconductor substrate, using a two-step etching technique in which dry etching and wet etching are performed successively. The exposed portion of the semiconductor substrate not over-etched is selectively oxidized to form a tunnel insulating film (second gate insulating film) having edge portions resistant to dielectric breakdown. Thereafter, a floating gate, a third gate insulating film, and a control gate are formed sequentially. The floating gate is patterned in such a way as to cover the entire tunnel insulating film or cross only a portion of an edge of the tunnel insulating film. The stress caused to the tunnel insulating film as a result of the oxidation process for forming the third gate insulating film is relieved, providing the tunnel insulating film with resistance to dielectric strength.

Abstract translation: 公开了一种长寿命的电可写和可擦除非易失性半导体存储器件。 存储器件按以下步骤制造。 在半导体衬底上形成第一栅极绝缘膜之后，在第一栅极绝缘膜中打开窗口，以使用执行干蚀刻和湿蚀刻的两步蚀刻技术来露出半导体衬底的一部分表面 依次。 未过蚀刻的半导体衬底的暴露部分被选择性地氧化以形成具有耐绝缘击穿的边缘部分的隧道绝缘膜（第二栅极绝缘膜）。 此后，依次形成浮栅，第三栅绝缘膜和控制栅。 浮栅被图案化以覆盖整个隧道绝缘膜或仅交叉隧道绝缘膜的边缘的一部分。 由于形成第三栅极绝缘膜的氧化工艺，隧道绝缘膜产生的应力得以缓解，为绝缘强度提供了隧道绝缘膜。

公开(公告)号：US5332924A

公开(公告)日：1994-07-26

申请号：US943473

申请日：1992-09-11

Applicant: Migaku Kobayashi

Inventor： Migaku Kobayashi

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/34 ,  H01L21/465

CPC classification number: H01L29/41725 ,  H01L21/76804 ,  H01L29/41775

Abstract: A semiconductor device having a superior step coverage of a layer formed inside or near a contact-hole is provided. An intermediate conductive layer is formed through an insulating layer on a lower conductive layer on a semiconductor substrate, and first, second and third inter-layer insulating layers are formed on the intermediate conductive layer. The third inter-layer insulating layer is selectively removed by an isotropic wet etching method thereby to form a through-hole extended to the second inter-layer insulating layer and having a large opening area. In performing this, the second inter-layer insulating layer acts to restrict the removal of the third inter-layer insulating layer in the thickness direction. Next, the first and second inter-layer insulating layers are selectively removed by an anisotropic dry etching method thereby to form a through-hole having a small opening area. The through-hole having a large opening area and the through-hole having a small opening area form a contact-hole. Subsequently, an upper conductive layer is formed on the third inter-layer insulating layer so as to be electrically connected to the lower conductive layer through the contact-hole.

Abstract translation: 提供了在接触孔内部或附近形成的层具有优异的台阶覆盖度的半导体器件。 通过半导体衬底上的下导电层上的绝缘层形成中间导电层，在中间导电层上形成第一，第二和第三层间绝缘层。 通过各向同性的湿蚀刻方法选择性地去除第三层间绝缘层，从而形成延伸到第二层间绝缘层并具有大的开口面积的通孔。 在这样做时，第二层间绝缘层用于限制第三层间绝缘层在厚度方向上的去除。 接下来，通过各向异性干蚀刻方法选择性地去除第一和第二层间绝缘层，从而形成具有小开口面积的通孔。 具有大开口面积的通孔和具有小开口面积的通孔形成接触孔。 随后，在第三层间绝缘层上形成上导电层，以便通过接触孔与下导电层电连接。

公开(公告)号：US5319238A

公开(公告)日：1994-06-07

申请号：US920734

申请日：1992-07-28

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L21/768 ,  H01L23/525 ,  H01L27/02 ,  H01L23/48 ,  H01L29/34 ,  H01L29/46

CPC classification number: H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation. The bottom electrodes of the antifuses are connected to the first-metal contacts. The overall capacitance associated with the antifuses is low, and hence the circuit is fast.

公开(公告)号：US5319229A

公开(公告)日：1994-06-07

申请号：US874497

申请日：1992-04-27

Applicant: Noriyuki Shimoji ,  Takanori Ozawa ,  Hironobu Nakao

Inventor： Noriyuki Shimoji ,  Takanori Ozawa ,  Hironobu Nakao

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/34 ,  H01L29/68 ,  H01L29/78

CPC classification number: H01L21/28202 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

Abstract: A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.

Abstract translation: 半导体非易失性存储器。 存储单元具有以下结构。 在P型硅衬底3中，设置有n +型源极26和n +型漏极28，两个区域形成沟道区30。在沟道区域30的顶部层叠有二氧化硅膜5，绝缘 由氮化物膜18a，18b和18c以及氧化物膜20a，20b和20c组成的层。 此外，在绝缘层的顶部，形成用作控制电极的多晶硅膜24。 通过使用存储单元和行选择晶体管，可以构成半导体非易失性存储器。

公开(公告)号：US5317179A

公开(公告)日：1994-05-31

申请号：US764019

申请日：1991-09-23

Applicant: Ling Chen ,  Tien-ler Lin ,  Albert Wu

Inventor： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68 ,  H01L29/34 ,  H01L29/78

CPC classification number: H01L29/66825 ,  H01L29/7883 ,  H01L27/115

Abstract: Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

Abstract translation: 公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。 浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。 还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。