公开(公告)号：US20040135210A1

公开(公告)日：2004-07-15

申请号：US10752705

申请日：2004-01-08

发明人： Takashi Noguchi ,  Mitsuo Soneda

IPC分类号： H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC分类号： H01L21/823814 ,  H01L21/823807

摘要： A field effect transistor of the present invention is formed in a strain effect semiconductor layer, represented by a strain effect silicon layer, formed in an upper layer of a semiconductor substrate. A source/a drain of the field effect transistor are formed only in the strain effect silicon layer. The field effect transistor may be formed as an nMOS transistor, and a pMOS transistor may be formed in the strain effect silicon layer while being isolated from the nMOS transistor through an isolation region. A logic circuit can be formed of these transistors. Although when an nMOS transistor or a pMos transistor is employed in an application requiring a high performance at a low voltage, there occurs a current leak because the junction of a source/a drain is positioned in a silicon germanium layer having a low band gap or formed at an interface of silicon/silicon germanium, the field effect transistor of the present invention prevents occurrence of such a current leak.

摘要翻译： 本发明的场效应晶体管形成在由半导体衬底的上层形成的应变效应硅层表示的应变效应半导体层中。 场效应晶体管的源极/漏极仅在应变效应硅层中形成。 场效应晶体管可以形成为nMOS晶体管，并且可以在应变效应硅层中形成pMOS晶体管，同时通过隔离区域与nMOS晶体管隔离。 逻辑电路可以由这些晶体管形成。 虽然当在低电压下需要高性能的应用中使用nMOS晶体管或pMos晶体管时，由于源极/漏极的结被定位在具有低带隙的硅锗层中而产生电流泄漏， 形成在硅/硅锗的界面处，本发明的场效应晶体管防止发生这种电流泄漏。

公开(公告)号：US20040135198A1

公开(公告)日：2004-07-15

申请号：US10623520

申请日：2003-07-22

申请人： Kabushiki Kaisha Toshiba

发明人： Yuuichiro Murahama

IPC分类号： H01L029/76

CPC分类号： H01L27/11526 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/11541

摘要： A semiconductor device according to an aspect of the present invention having a first gate insulating film formed in a first active region of a semiconductor substrate and having a first film thickness, and a second gate insulating film formed in a second active region of the semiconductor substrate and having a second film thickness smaller than the first film thickness, wherein a semiconductor substrate surface in the first active region is lower than that in the second active region is provided.

摘要翻译： 根据本发明的一个方面的半导体器件具有形成在半导体衬底的第一有源区中并具有第一膜厚度的第一栅极绝缘膜和形成在半导体衬底的第二有源区中的第二栅极绝缘膜 并且具有小于第一膜厚度的第二膜厚度，其中提供第一有源区中的半导体衬底表面低于第二有源区中的半导体衬底表面。

公开(公告)号：US20040135182A1

公开(公告)日：2004-07-15

申请号：US10705680

申请日：2003-11-10

发明人： Hyeong-Geun An ,  Sang-Woo Lee ,  Hyoung-Joon Kim

IPC分类号： H01L029/76

CPC分类号： H01L28/75 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

摘要： Ferroelectric capacitors include a support insulating film on an integrated circuit substrate and having a trench therein. A lower electrode is on sidewalls and a bottom surface of the trench. A seed conductive film covers the lower electrode. A ferroelectric film is provided on the support insulating film and the seed conductive film and an upper electrode is provided on the ferroelectric film. The lower electrode may fill the trench and the ferroelectric film may extend over all of the seed conductive film and the support insulating film adjacent the seed conductive film.

摘要翻译： 铁电电容器包括集成电路基板上的支撑绝缘膜并且在其中具有沟槽。 下电极位于沟槽的侧壁和底表面上。 种子导电膜覆盖下电极。 在支撑绝缘膜和种子导电膜上设置铁电体膜，在铁电体膜上设置上电极。 下电极可以填充沟槽，并且铁电膜可以延伸到与种子导电膜相邻的种子导电膜和支撑绝缘膜上。

公开(公告)号：US20040132239A1

公开(公告)日：2004-07-08

申请号：US10736943

申请日：2003-12-16

申请人： CHARTERED SEMICONDUCTOR MANUFACTURING LTD.

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L021/8238 ,  H01L029/76

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

公开(公告)号：US20040129988A1

公开(公告)日：2004-07-08

申请号：US10336563

申请日：2003-01-03

发明人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

IPC分类号： H01L031/119 ,  H01L031/062 ,  H01L029/94 ,  H01L021/336 ,  H01L029/76 ,  H01L031/113

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/2807

摘要： The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).

摘要翻译： 本发明涉及一种PMOS晶体管的形成，其中一层硅或SiGe抑制p型掺杂剂进入下面的栅介质层。 可以将p型掺杂剂添加到覆盖硅或SiGe层的栅电极材料中，并且可以向硅或SiGe层扩散。 硅或SiGe层可以形成为约5至120纳米的厚度，并掺杂有例如铟（In）的掺杂剂，以阻止p型掺杂剂通过硅或SiGe层。 掺杂剂可以在硅或SiGe层的界面附近与硅介电材料的下层之间的硅或SiGe层内具有峰值浓度。 允许栅电极掺杂有p型掺杂剂（例如硼）有助于以具有期望值（例如，与约4.8至约5.6电子伏特的费米能级一致）的相关功函数形成晶体管。

公开(公告)号：US20040129981A1

公开(公告)日：2004-07-08

申请号：US10741751

申请日：2003-12-19

发明人： Young-Pil Kim ,  Beom-Jun Jin ,  Hyoung-Joon Kim ,  Byeong-Yun Nam

IPC分类号： H01L029/76

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823475

摘要： An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

摘要翻译： 集成电路器件包括其中形成有源极区和漏极区的衬底。 在源极区域和漏极区域之间的衬底上设置栅极图案。 下焊盘层设置在源极区域和/或漏极区域上并且包括与衬底相同的晶体结构。 导电层设置在下焊盘层上，使得导电层的至少一部分设置在下焊盘层和栅极图案之间。 绝缘层设置在栅极图案与下焊盘层和导电层之间以及导电层和基板之间。

公开(公告)号：US20040129974A1

公开(公告)日：2004-07-08

申请号：US10728682

申请日：2003-12-05

申请人： Hitachi, Ltd. ,  Texas Instruments Incorporated

发明人： Goro Kitsukawa ,  Takesada Akiba ,  Hiroshi Otori ,  William R. McKee ,  Jeffrey E. Koelling ,  Troy H. Herndon

IPC分类号： H01L029/76

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

摘要翻译： 一种用于在阵列型集成电路上提供网状电源和信号总线系统的方法和装置，其使电路的尺寸最小化。 与现有技术不同，用于网状系统的通孔被放置在电池阵列以及外围电路中。 网格系统的功率和信号总线跨阵列在垂直和水平方向上运行，使得所有垂直总线位于一个金属层中，并且所有水平总线位于另一个金属层中。 使用位于阵列中的通孔将一层的总线连接到另一层的适当总线。 一旦连接，总线延伸到适当的感应放大器驱动器。 通过实现分级字线结构的改进的子解码器电路来促进该方法和装置。

公开(公告)号：US20040129962A1

公开(公告)日：2004-07-08

申请号：US10738730

申请日：2003-12-16

发明人： Tsutomu Asakawa

IPC分类号： H01L029/76

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/55

摘要： A semiconductor device embodiment may include a plurality of cells each including a transistor therein, the cells also each including a first capacitor electrode therein, the first capacitor electrodes being positioned on an insulating layer, the first capacitor electrodes in adjacent cells being separated from each other. The device may also include partitioning members on the insulation layer, wherein the partitioning members are positioned to separate the cells from one another, and the partitioning members include an upper surface thereon. The device also may include an organic layer on the first capacitor electrodes between the partitioning members, wherein the organic layer is not positioned in contact with the upper surface of the partitioning members. The device may also include a continuous second capacitor electrode on the organic layer, the second capacitor electrode layer formed to be a common electrode for cells. In another aspect, the organic layer may be capable of a polarization inversion by exposure to an electric field. In another aspect, the partitioning members may include first and second layers, the first layer being formed from a material having an affinity for an organic solution used to form the organic layer, the second layer being formed from a material having a non-affinity for the organic solution used to form the organic layer.

摘要翻译： 半导体器件实施例可以包括多个单元，每个单元均包括晶体管，单元还各自包括第一电容器电极，第一电容器电极位于绝缘层上，相邻单元中的第一电容器电极彼此分离 。 该装置还可以包括在绝缘层上的分隔构件，其中分隔构件被定位成将细胞彼此分开，并且分隔构件包括其上的上表面。 该装置还可以在分隔构件之间的第一电容器电极上包括有机层，其中有机层不与分隔构件的上表面接触。 该器件还可以在有机层上包括连续的第二电容器电极，第二电容器电极层形成为用于电池的公共电极。 在另一方面，有机层可以通过暴露于电场而能够进行极化反转。 在另一方面，分隔构件可以包括第一和第二层，第一层由对用于形成有机层的有机溶液具有亲和性的材料形成，第二层由具有非亲和性的材料形成 用于形成有机层的有机溶液。

公开(公告)号：US20040129960A1

公开(公告)日：2004-07-08

申请号：US10740501

申请日：2003-12-22

发明人： Junya Maruyama ,  Toru Takayama ,  Yumiko Ohno ,  Shunpei Yamazaki

IPC分类号： H01L029/76

CPC分类号： H01L27/1218 ,  H01L21/76251 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/1266 ,  H01L29/78603 ,  H01L33/24 ,  H01L33/44 ,  H01L33/56 ,  H01L33/62 ,  H01L2221/68368

摘要： A technique for forming a TFT element over a substrate having flexibility typified by a flexible plastic film is tested. When a structure in which a light-resistant layer or a reflective layer is employed to prevent the damage to the delamination layer, it is difficult to fabricate a transmissive liquid crystal display device or a light emitting device which emits light downward. A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed.

摘要翻译： 测试了以柔性塑料膜为代表的柔性基板上形成TFT元件的技术。 当采用耐光层或反射层以防止对分层的损害的结构时，难以制造向下发光的透射型液晶显示装置或发光装置。 在基板上形成金属膜的状态下，通过物理手段或机械装置分离基板和分层膜，以及包含包含金属的氧化物膜和包含硅的膜的分层，其形成在 提供金属膜。 具体地说，通过在金属膜上形成包含金属的氧化物层而获得的TFT; 通过热处理使氧化层结晶; 并且在氧化物层的一层或氧化物层的界面上形成分层。

公开(公告)号：US20040129959A1

公开(公告)日：2004-07-08

申请号：US10738316

申请日：2003-12-17

发明人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

IPC分类号： H01L021/336 ,  H01L029/76 ,  H01L031/113 ,  H01L021/3205 ,  H01L031/062 ,  H01L021/4763

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

摘要翻译： 半导体器件包括其中具有凹部的半导体衬底。 栅极绝缘体设置在凹部中的基板上。 该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。 源极/漏极区域设置在邻近凹部的衬底中。 凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。 源极/漏极区域可以包括邻近凹部的较轻掺杂部分。 还讨论了相关制造方法。