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公开(公告)号：US20230207019A1
公开(公告)日：2023-06-29
申请号：US18081114
申请日：2022-12-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Lawrence Celso Miranda , Sheyang Ning , Jeffrey S. McNeil , Tomoko Ogura Iwasaki
CPC classification number: G11C16/102 , G11C16/08 , G11C16/24
Abstract: Control logic in a memory device causes a boost voltage to be applied one or more times to a plurality of unselected wordlines of a block of the memory array, the block comprising a plurality of sub-blocks, and the boost voltage to boost a channel potential of each of the plurality of sub-blocks by an amount each time the boost voltage is applied. The control logic further selectively discharges the amount of boost voltage from one or more of the plurality of sub-blocks after each time the boost voltage is applied according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. Additionally, the control logic causes a single programming pulse to be applied to one or more selected wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.
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公开(公告)号：US20230207009A1
公开(公告)日：2023-06-29
申请号：US17778095
申请日：2021-12-31
Applicant: DALIAN UNIVERSITY OF TECHNOLOGY
Inventor： Jianwei ZHANG
Abstract: An enhanced TL-TCAM lookup-table hardware search engine includes a plurality of enhanced TL-TCAM cell circuits. There are m enhanced TL-TCAM cells circuits connected in parallel to form a sub-segment circuit. The word line WL, match line ML and ML_x of each enhanced TL-TCAM cell circuit in the sub-segment circuit are respectively short-connected together, the match line ML is connected to the drain electrode of an N-type transistor N15, ML_x is connected to the gate electrode of the N-type transistor N15, and the source electrode of the N-type transistor N15 is connected to ground, ML_x is connected to the drain electrode of an N-type transistor N14, the source electrode of the N-type transistor N14 is connected to ground, and the gate electrode of the N-type transistor N14 is connected to the signal line OneX_in-Sement_b, a plurality of sub-segment circuits are connected in parallel to form a word circuit.
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公开(公告)号：US11682461B2
公开(公告)日：2023-06-20
申请号：US17691821
申请日：2022-03-10
Applicant: Ferroelectric Memory GmbH
Inventor： Menno Mennenga , Johannes Ocker
Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.
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84.发明公开公开(公告)号：US20230186996A1
公开(公告)日：2023-06-15
申请号：US17549471
申请日：2021-12-13
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Dengtao Zhao , Sarath Puthenthermadam , Jiahui Yuan
CPC classification number: G11C16/102 , G11C16/26 , G11C16/30 , G11C16/24 , G11C7/04
Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
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公开(公告)号：US11670384B2
公开(公告)日：2023-06-06
申请号：US17587998
申请日：2022-01-28
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Weirong Chen , Qiang Tang
Abstract: A bias circuit, a memory system, and a method of boosting a voltage level of a first bit line are provided. The bias circuit includes a first current generator, a second current generator, and a bit line bias generator. The first current generator is configured to generate a first replica charging current according to a charging current flowing through a voltage bias transistor. The second current generator is configured to generate a first replica cell current according to a cell current flowing through a common source transistor. The bit line bias generator is coupled to a first page buffer, the first current generator, and the second current generator, and configured to generate a bit line bias voltage, supplied to the first page buffer, according to a comparison of the first replica charging current and the first replica cell current.
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Patent Agency Ranking
公开(公告)号：US11670381B2
公开(公告)日：2023-06-06
申请号：US17313249
申请日：2021-05-06
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
CPC classification number: G11C16/26 , G11C16/04 , G11C16/0483 , G11C16/28 , G11C16/349 , G11C29/021 , G11C29/028 , G11C16/08 , G11C16/24 , G11C2207/2254
Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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公开(公告)号：US20230171958A1
公开(公告)日：2023-06-01
申请号：US17565484
申请日：2021-12-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Hsun Shuai , Yu-Jen Yeh , Chih-Jung Chen
IPC: H01L27/11526 , G11C16/28 , G11C16/24
CPC classification number: H01L27/11526 , G11C16/28 , G11C16/24
Abstract: A semiconductor memory device includes a substrate, a plurality of memory cells and at least one strap cell between the plurality of memory cells disposed along a first direction, a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the strap cell. The at least one source line contact is aligned with the plurality of BL contacts in the first direction.
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公开(公告)号：US20230170031A1
公开(公告)日：2023-06-01
申请号：US18159882
申请日：2023-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk CHOI , Sangwan Nam , Jaeduk Yu , Yohan Lee
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511 , H10B41/27
Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.
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公开(公告)号：US11657874B2
公开(公告)日：2023-05-23
申请号：US17480858
申请日：2021-09-21
Applicant: KIOXIA CORPORATION
Inventor： Sanad Bushnaq , Noriyasu Kumazaki , Masashi Yamaoka
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/14 , G11C16/24 , H01L27/11556 , G11C16/10 , G11C16/26
Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.
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公开(公告)号：US20230154548A1
公开(公告)日：2023-05-18
申请号：US18156955
申请日：2023-01-19
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Siyuan WANG , Jin Yong OH , Yu WANG , Ye TIAN , Zhichao DU , Xiaojiang GUO
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/24 , H10B43/27
Abstract: A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.
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