公开(公告)号：US10061675B2

公开(公告)日：2018-08-28

申请号：US15384378

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F9/312 ,  G06F12/12 ,  G06F13/38 ,  G06F13/36 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10

CPC classification number: G06F11/3037 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/27 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F2212/452 ,  G06F2212/602

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US10061584B2

公开(公告)日：2018-08-28

申请号：US15060404

申请日：2016-03-03

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Aaron L. Smith

IPC: G06F9/312 ,  G06F9/44 ,  G06F9/30 ,  G06F15/80 ,  G06F9/32 ,  G06F9/38 ,  G06F9/26 ,  G06F11/36 ,  G06F12/0862 ,  G06F9/35 ,  G06F12/1009 ,  G06F13/42 ,  G06F15/78 ,  G06F9/46 ,  G06F9/52 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0806

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction. The memory access instruction associated with the instruction identification is nullified. The memory access instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified memory access instruction, a subsequent memory access instruction from the first instruction block is executed.

公开(公告)号：US10055878B2

公开(公告)日：2018-08-21

申请号：US15252436

申请日：2016-08-31

Applicant: Siemens Healthcare GmbH

Inventor： Klaus Engel ,  Jana Martschinke

IPC: G06T15/06 ,  G06T15/08 ,  G06F12/0897 ,  G06F12/0875

CPC classification number: G06T15/06 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/455 ,  G06T15/08 ,  G06T2207/10081 ,  G06T2207/10088 ,  G06T2207/10104 ,  G06T2207/10108 ,  G06T2207/10132 ,  G06T2207/20024

Abstract: A method of visualizing a three-dimensional object from a data volume is disclosed. In an embodiment, the method includes computing an irradiance cache for the data volume; and applying the irradiance cache during rendering of a three-dimensional image from the data volume. In an embodiment, entries of the irradiance cache are organized in a uniform grid.

公开(公告)号：US20180211713A1

公开(公告)日：2018-07-26

申请号：US15479315

申请日：2017-04-05

Applicant: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED ,  LITE-ON TECHNOLOGY CORPORATION

Inventor： Shih-Jia Zeng ,  Jen-Chien Fu

IPC: G11C16/26 ,  G06F12/0875

CPC classification number: G11C16/26 ,  G06F12/0875 ,  G06F2212/60

Abstract: A solid state storage device includes a non-volatile memory and a controlling circuit. In a first read retry process, the controlling circuit judges whether an information corresponding to a first block of the non-volatile memory is recorded in the cache table. If the information is not recorded in the cache table, the controlling circuit sequentially provides plural predetermined retry read voltage sets to the non-volatile memory according to a sequence of the plural predetermined retry read voltage sets in the retry table and performs a read retry operation. If a read data of the first block is successfully decoded through the read retry operation according to a first predetermined retry read voltage set of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records the first predetermined retry read voltage set into the cache table.

公开(公告)号：US20180196824A1

公开(公告)日：2018-07-12

申请号：US15402119

申请日：2017-01-09

Applicant: Splunk, Inc.

Inventor： Ledion Bitincka ,  Alexandros Batsakis ,  Paul J. Lucas ,  Nicholas Robert Romito

IPC: G06F17/30

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0873 ,  G06F17/30106 ,  G06F17/30132 ,  G06F17/30864 ,  G06F17/30902 ,  G06F2212/1021 ,  G06F2212/45 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/6028

Abstract: Embodiments are disclosed for performing cache aware searching. In response to a search query, a first bucket and a second bucket in remote storage for processing the search query. A determination is made that a first file in the first bucket is present in a cache when the search query is received. In response to the search query, a search is performed using the first file based on the determination that the first file is present in the cache when the search query is received, and the search is performed using a second file from the second bucket once the second file is stored in the cache.

公开(公告)号：US20180181372A1

公开(公告)日：2018-06-28

申请号：US15618636

申请日：2017-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donguk MOON

IPC: G06F5/14 ,  G06F1/32 ,  G06F12/0831 ,  G06F12/0875

CPC classification number: G06F5/14 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0831 ,  G06F12/0875 ,  G06F2205/126 ,  G06F2212/621 ,  Y02D10/128 ,  Y02D10/152

Abstract: An electronic device according to some example embodiments includes a clock management circuit configured to control a clock signal and a processor circuit directly connected to the clock management circuit and configured to provide a clock control request for the clock signal to the clock management circuit according to an operation status of the processor circuit.

公开(公告)号：US10007616B1

公开(公告)日：2018-06-26

申请号：US15062448

申请日：2016-03-07

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  David J. Williamson ,  Jonathan J. Tyler ,  Mary D. Brown

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0831 ,  G06F12/128

CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F12/0862 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/502

Abstract: In an embodiment, an apparatus includes a cache memory and a control circuit. The control circuit may be configured to pre-fetch and store a first quantity of instruction data in response to a determination that a first pre-fetch operation request is received after a reset and prior to a first end condition. The first end condition may depend on an amount of unused storage in the cache memory. The control circuit may be further configured to pre-fetch and store a second quantity of instruction data in response to a determination that a second pre-fetch operation request is received after the first end condition. The second quantity may be less than the first quantity.

公开(公告)号：US10007610B2

公开(公告)日：2018-06-26

申请号：US15826961

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shay H. Akirav ,  Lior Aronovich

IPC: G06F12/08 ,  G06F3/06 ,  G06F17/30 ,  G06F12/0846 ,  G06F12/0875

CPC classification number: G06F12/0848 ,  G06F3/0619 ,  G06F3/0641 ,  G06F3/067 ,  G06F12/0875 ,  G06F16/1752 ,  Y02D10/13

Abstract: Input data is partitioned into data chunks and digest values are calculated for each of the data chunks. The positions of similar repository data are found in a repository of data for each of the data chunks. The input digests of the input data are matched with the repository digests contained in the global digests cache for locating data matches. A sample of the repository digests is loaded into a search mechanism within the global digests cache. The positions of the similar repository data are used to locate and linearly load into the global digests cache, digests and digest block boundaries of the similar repository data in a sequence corresponding to a placement order of calculated values of the digests of the similar repository data.

公开(公告)号：US10007543B2

公开(公告)日：2018-06-26

申请号：US14309794

申请日：2014-06-19

Applicant: VMware, Inc.

Inventor： Rishi Bidarkar ,  Hari Sivaraman ,  Banit Agrawal

IPC: G06F9/455 ,  G06F12/0802

CPC classification number: G06F9/45558 ,  G06F12/0802 ,  G06F12/0875 ,  G06F2009/45583 ,  G06F2212/401 ,  G06F2212/455 ,  G06T2200/28

Abstract: Exemplary methods, apparatuses, and systems receive a first instruction set from a first virtual machine (VM), the first instruction set including a request to perform an operation on an input. A first identifier is generated based upon the operation and the input. The first identifier is mapped to a stored copy of the input, the operation, and an output resulting from a processor performing the operation. In response to receiving a second instruction set from a second VM, a second identifier is generated based upon the input and operation received within the second instruction set. In response to determining that the second identifier matches the stored first identifier, it is further determined that the input and operation of the first instruction set matches the input and operation of the second instruction set. A copy of the stored output is returned to the second VM.

公开(公告)号：US20180174269A1

公开(公告)日：2018-06-21

申请号：US15895115

申请日：2018-02-13

Applicant: Imagination Technologies Limited

Inventor： Steven John FISHWICK ,  John HOWSON

IPC: G06T1/20 ,  G06F12/0815 ,  G06T15/00 ,  G06T1/60 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/126

CPC classification number: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/1021 ,  G06F2212/302 ,  G06F2212/45 ,  G06F2212/70 ,  G06T1/60 ,  G06T15/00 ,  G06T15/005

Abstract: A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the indicator for a graphics data item indicates the number of tiles with which that graphics data item is associated. The graphics data items are evicted from the cache in accordance with the indicators of the graphics data items. For example, the indicator for a graphics data item may be a count of the number of tiles with which that graphics data item is associated, whereby the graphics data item(s) with the lowest count(s) is (are) evicted from the cache.