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    Semiconductor integrated circuit with a test circuit for input buffer threshold
    81.
    发明授权
    Semiconductor integrated circuit with a test circuit for input buffer threshold 失效
    半导体集成电路具有输入缓冲阈值的测试电路

    公开(公告)号：US5633599A

    公开(公告)日：1997-05-27

    申请号：US509616

    申请日：1995-07-31

    申请人： Shuji Kubota

    发明人： Shuji Kubota

    IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/003

    CPC分类号： G01R31/31715 ,  G01R31/3004 ,  G01R31/31712

    摘要： In a semiconductor integrated circuit provided with a circuit for testing an input buffer threshold voltage, an output node of a first logic gate having its output logic value determined by an output signal of an input buffer, and an output node of a second logic gate having its output logic value determined by a condition setting signal from an external source, are connected to a common signal line. When a standardized voltage for discriminating the threshold voltage is applied to the input buffer, if the input buffer malfunctions, the output signal of the first logic gate collides with the output signal of the second logic gate on the common signal line, so that a power supply current greatly increases.

    摘要翻译： 在设置有用于测试输入缓冲器阈值电压的电路的半导体集成电路中，具有由输入缓冲器的输出信号确定的其输出逻辑值的第一逻辑门的输出节点和具有第二逻辑门的​​输出节点， 其由来自外部源的条件设置信号确定的输出逻辑值连接到公共信号线。 当用于识别阈值电压的标准化电压被施加到输入缓冲器时，如果输入缓冲器发生故障，则第一逻辑门的输出信号与公共信号线上的第二逻辑门的​​输出信号相冲突，使得功率 电源电流大大增加。

    Analog multi-channel probe system
    82.
    发明授权
    Analog multi-channel probe system 失效
    模拟多通道探头系统

    公开(公告)号：US5418470A

    公开(公告)日：1995-05-23

    申请号：US139651

    申请日：1993-10-22

    申请人： Thomas P. Dagostino ,  Arnold M. Frisch

    发明人： Thomas P. Dagostino ,  Arnold M. Frisch

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185

    CPC分类号： G01R31/318572 ,  G01R31/2884 ,  G01R31/31712 ,  G01R31/31715

    摘要： A programmable analog multi-channel probe system is embedded within a device under test for coupling test points to external measurement points of the device under test. Programmable input buffer amplifiers are coupled to the test points to couple the data at those points to their outputs when enabled. The data from the input buffer amplifiers are input to respective routers to provide a plurality of outputs. Each common output from the routers is coupled as an input to an output buffer amplifier that provides the data as an output when enabled. The data at the output of the output buffer amplifiers is converted to a differential signal for transmission to the external measurement point by differential input/output amplifiers that have a reference level, selected from a plurality of reference levels including an internal reference level, as an input for comparison with the data from the output buffer amplifiers. A termination circuit may be provided for each output to provide appropriate impedance interface with the measurement points.

    摘要翻译： 可编程模拟多通道探头系统嵌入在被测器件内，将测试点耦合到被测器件的外部测量点。 可编程输入缓冲放大器耦合到测试点，以在启用时将这些点处的数据耦合到其输出。 来自输入缓冲放大器的数据被输入到相应的路由器以提供多个输出。 来自路由器的每个公共输出作为输入耦合到输出缓冲放大器，其在启用时提供数据作为输出。 输出缓冲放大器的输出端的数据被转换为差分信号，以通过差分输入/输出放大器传输到外部测量点，差分输入/输出放大器具有从包括内部参考电平的多个参考电平中选择的参考电平，作为 输入与来自输出缓冲放大器的数据进行比较。 可以为每个输出提供终端电路，以向测量点提供适当的阻抗接口。

    Method for wafer scale testing of redundant integrated circuit dies
    83.
    发明授权
    Method for wafer scale testing of redundant integrated circuit dies 失效
    冗余集成电路管芯晶圆规模测试方法

    公开(公告)号：US5053700A

    公开(公告)日：1991-10-01

    申请号：US532059

    申请日：1990-06-01

    申请人： William J. Parrish

    发明人： William J. Parrish

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66

    CPC分类号： H01L22/22 ,  G01R31/2831 ,  G01R31/31712 ,  G01R31/31715 ,  G01R31/318505 ,  G01R31/318511 ,  G06F11/26 ,  G11C29/006 ,  G06F11/2273 ,  H01L2924/0002

    摘要： A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation. Additionally, line protection circuits are provided to prevent destruction of the integrated circuit dies should shorting occur during dicing. The integrated circuit dies and wafer scale test system may optionally be partitioned into several separate groups to prevent faults in the interchip multiplexor system from rendering the entire wafer useless.

    摘要翻译： 用于测试形成在半导体晶片上的冗余集成电路管芯的晶片级测试系统包括晶片上形成的晶片刻度测试焊盘和用于将施加到晶片尺度测试焊盘上的测试信号引导到各个集成电路管芯的芯片间复用器装置。 芯片间复用器装置包括用于接收来自晶片焊盘的测试信号的输入/输出缓冲电路，并将测试信号施加到被路由到各个电路管芯的选定的芯片间多路复用器线路。 所述集成电路管芯上的输出焊盘的读出通过输入/输出缓冲电路返回到晶片测试焊盘，以提供测试输出信号。 在集成电路裸片接触焊盘和芯片间复用器线之间的切割通道之间提供低横截面连接装置，以避免在切割操作期间的短路。 此外，提供线路保护电路以防止在切割期间发生短路时集成电路芯片的破坏。 集成电路管芯和晶片刻度测试系统可以可选地分成几个单独的组，以防止芯片间复用器系统中的故障使整个晶片无用。

    Die-to-die and chip-to-chip connectivity monitoring
    86.
    发明授权
    Die-to-die and chip-to-chip connectivity monitoring 有权

    公开(公告)号：US12013800B1

    公开(公告)日：2024-06-18

    申请号：US18209685

    申请日：2023-06-14

    申请人： PROTEANTECS LTD.

    发明人： Eyal Fayneh ,  Guy Redler ,  Evelyn Landman

    IPC分类号： G06F13/20 ,  G01R31/317

    CPC分类号： G06F13/20 ,  G01R31/31712 ,  G01R31/31725 ,  G06F2213/40

    摘要： An input/output (I/O) sensor is provided for a multi-IC (Integrated Circuit) module. The I/O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I/O block, an IC, and/or a multi-IC module.

    SYSTEM AND METHOD OF MONITORING PERFORMANCE OF AN ELECTRONIC DEVICE
    88.
    发明公开
    SYSTEM AND METHOD OF MONITORING PERFORMANCE OF AN ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230184830A1

    公开(公告)日：2023-06-15

    申请号：US17988989

    申请日：2022-11-17

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sunwook KIM ,  Heeseong LEE ,  Myonghoon YANG ,  Manhwee JO ,  Wooil KIM

    IPC分类号： G01R31/317

    CPC分类号： G01R31/31718 ,  G01R31/31723 ,  G01R31/31712

    摘要： A system of monitoring performance of an electronic device including: a plurality of performance monitoring circuits included in an electronic device, wherein the plurality of performance monitoring circuits are configured to generate a plurality of monitor output signals including performance data of the electronic device; a monitoring bus configured to receive the plurality of monitor output signals and generate a. bus output signal by interleaving the performance data included in the plurality of monitor output signals; and an embedded trace router configured to receive the bus output signal and store, in a memory device included in the electronic device, the performance data. included in the bus output signal,