公开(公告)号：US20230184830A1

公开(公告)日：2023-06-15

申请号：US17988989

申请日：2022-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunwook KIM ,  Heeseong LEE ,  Myonghoon YANG ,  Manhwee JO ,  Wooil KIM

IPC: G01R31/317

CPC classification number: G01R31/31718 ,  G01R31/31723 ,  G01R31/31712

Abstract: A system of monitoring performance of an electronic device including: a plurality of performance monitoring circuits included in an electronic device, wherein the plurality of performance monitoring circuits are configured to generate a plurality of monitor output signals including performance data of the electronic device; a monitoring bus configured to receive the plurality of monitor output signals and generate a. bus output signal by interleaving the performance data included in the plurality of monitor output signals; and an embedded trace router configured to receive the bus output signal and store, in a memory device included in the electronic device, the performance data. included in the bus output signal,

公开(公告)号：US20250147570A1

公开(公告)日：2025-05-08

申请号：US18916306

申请日：2024-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yooseok SON ,  Sehun KIM ,  Kangtae CHO ,  Wonsoo KIM ,  Saena YUK ,  Heeseong LEE ,  Younsik CHOI

IPC: G06F1/3228 ,  G06F1/3209

Abstract: Provided are a semiconductor system for reducing idle power when a specific block is idle and an operating method thereof. The semiconductor system includes a first block, the first block including a plurality of intellectual property (IP) blocks each configured to generate active information, and a first control logic configured to determine an active state of each of the plurality of IP blocks based on the active information and, in response to the active states of the plurality of IP blocks all being idle states, perform a power gating operation on the first block.

公开(公告)号：US20250147566A1

公开(公告)日：2025-05-08

申请号：US18915876

申请日：2024-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yooseok SON ,  Sehun KIM ,  Heeseong LEE

IPC: G06F1/3206

Abstract: A semiconductor system including: a memory to store data; a first master intellectual property (IP) block configured to generate a first wakeup signal; a first bus block configured to generate a second wakeup signal while performing a wakeup operation in response to the first wakeup signal; a second bus block configured to generate a third wakeup signal while performing the wakeup operation in response to the second wakeup signal; and a third bus block configured to perform data communication with the memory and perform the wakeup operation in response to the third wakeup signal.

公开(公告)号：US20230269205A1

公开(公告)日：2023-08-24

申请号：US18311181

申请日：2023-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongmin JO ,  Heeseong LEE ,  Jaehyun KIM ,  Jinsu JUNG

IPC: H04L49/90 ,  H04L49/00 ,  H04L49/109

CPC classification number: H04L49/9094 ,  H04L49/3027 ,  H04L49/9021 ,  H04L49/109

Abstract: A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.