公开(公告)号：US11037957B2

公开(公告)日：2021-06-15

申请号：US16884898

申请日：2020-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsueh-Chih Chou ,  Chia Hao Tu ,  Sang Hoo Dhong ,  Lee-Chung Lu ,  Li-Chun Tien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

公开(公告)号：US11030372B2

公开(公告)日：2021-06-08

申请号：US16659351

申请日：2019-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pin-Dai Sue ,  Chin-Chou Liu ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Lee-Chung Lu ,  Yen-Hung Lin ,  Li-Chun Tien ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.

公开(公告)号：US11012073B2

公开(公告)日：2021-05-18

申请号：US16936281

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lun Ou ,  Jerry Chang Jui Kao ,  Lee-Chung Lu ,  Ruei-Wun Sun ,  Shang-Chih Hsieh ,  Ji-Yung Lin ,  Wei-Hsiang Ma ,  Yung-Chen Chien

IPC: H03K19/0185 ,  H03K3/037

Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.

公开(公告)号：US11012057B2

公开(公告)日：2021-05-18

申请号：US16294726

申请日：2019-03-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kai-Chi Huang ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Wei-Hsiang Ma ,  Yung-Chen Chien

IPC: H03K3/037 ,  G06F1/3237 ,  H03K19/00 ,  H03K3/356

Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.

公开(公告)号：US10741540B2

公开(公告)日：2020-08-11

申请号：US16204678

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chien-Ying Chen ,  Lee-Chung Lu ,  Li-Chun Tien ,  Ta-Pen Guo

IPC: H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  G06F30/392

Abstract: A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first direction, extending a second portion of the boundary away from the first portion in a second direction perpendicular to the first direction, the second portion being contiguous with the first portion, and extending a third portion of the boundary away from the first portion in the second direction, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region away from the first portion in a third direction opposite to the second direction. The layout diagram is stored on a non-transitory computer-readable medium.

公开(公告)号：US10740531B2

公开(公告)日：2020-08-11

申请号：US15792289

申请日：2017-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Meng-Hung Shen ,  Shang-Chih Hsieh ,  Chi-Yu Lu

IPC: G06F30/394 ,  H01L27/118 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.

公开(公告)号：US10003342B2

公开(公告)日：2018-06-19

申请号：US14740499

申请日：2015-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Lee-Chung Lu ,  Meng-Hsueh Wang ,  Shang-Chih Hsieh ,  Henry Huang ,  Ji-Yung Lin

IPC: H03K19/21

CPC classification number: H03K19/21

Abstract: A compressor circuit includes a plurality of inputs, a sum output, and a plurality of XOR circuits. Each XOR circuit of the plurality of XOR circuits includes first, second and third inputs, and a first output. The XOR circuit is configured to generate a logic value A⊕B⊕C at the first output, where A, B and C are logic values at the corresponding first, second and third inputs, and “⊕” is the XOR logic operation. The plurality of XOR circuits includes first and second XOR circuits. The first, second and third inputs of the first XOR circuit are coupled to corresponding inputs among the plurality of inputs of the compressor circuit. The first output of the first XOR circuit is coupled to the first input of the second XOR circuit. The first output of the second XOR circuit is coupled to the sum output.

公开(公告)号：US09754073B2

公开(公告)日：2017-09-05

申请号：US15237286

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Yu-Hsiang Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC: G06F17/50 ,  G03F7/00

CPC classification number: G06F17/5081 ,  G03F7/0035 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

公开(公告)号：US09691666B2

公开(公告)日：2017-06-27

申请号：US15149925

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lee-Chung Lu ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC: H01L21/82 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/02 ,  H01L21/768 ,  H01L29/423 ,  H01L21/3205 ,  H01L29/06 ,  H01L27/32

CPC classification number: H01L21/823475 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/823418 ,  H01L27/0207 ,  H01L27/326 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/4238

Abstract: An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.

公开(公告)号：US09543193B2

公开(公告)日：2017-01-10

申请号：US14833949

申请日：2015-08-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lee-Chung Lu ,  Yuan-Te Hou ,  Shyue-Shyh Lin ,  Li-Chun Tien ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/7681 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch.

Abstract translation: 集成电路结构包括半导体衬底和半导体衬底上的第一金属层。 第一金属层具有第一最小间距。 第二金属层在第一金属层之上。 第二金属层具有小于第一最小间距的第二最小间距。