公开(公告)号：US06434661B1

公开(公告)日：2002-08-13

申请号：US09640518

申请日：2000-08-17

Applicant: Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

Inventor： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

IPC: G06F1300

CPC classification number: G11C7/1006 ,  G06F12/0893 ,  G11C7/103 ,  G11C7/1045 ,  G11C11/005 ,  G11C2207/2254

Abstract: A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal. The latch circuit provides data at a first clock cycle of a clock signal when the command data has a first value and provides data at a second clock cycle of the clock signal, which is later than the first clock cycle, when the command data has a second value.

Abstract translation: 半导体存储器件具有用作高速缓冲存储器的静态随机存取存储器（SRAM）和用作主存储器的动态随机存取存储器（DRAM）。 双向数据传输电路被布置用于在SRAM和DRAM之间传送数据块。 提供了一个命令寄存器来保存命令数据以设置诸如存储器件的数据输出模式的操作模式。 数据输出模式可以包括根据存储器件的数据输入端子处的数据组合选择的透明模式，锁存模式和注册模式。 用于提供选择的数据输出模式的输出电路包括用于响应于时钟信号在读取数据总线上锁存数据的输出锁存电路，以及用于将数据从输出锁存器输出到数据输出端的输出缓冲器。 当命令数据具有第一值时，锁存电路以时钟信号的第一时钟周期提供数据，并且当命令数据具有第一时钟周期时，提供比第一时钟周期晚的时钟信号的第二时钟周期的数据 第二个值。

公开(公告)号：US06356484B2

公开(公告)日：2002-03-12

申请号：US09480006

申请日：2000-01-10

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Ishizuka ,  Tsukasa Saika

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Ishizuka ,  Tsukasa Saika

IPC: G11C1100

CPC classification number: G11C8/00 ,  G06F12/0893 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02D10/13

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

Abstract translation: 半导体存储器件包括DRAM，SRAM和设置在SRAM和DRAM之间的双向传输门电路。 SRAM阵列包括多组字线。 在SRAM阵列的每行中提供每组，并且每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器。 半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路。 从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。 数据写入路径和数据读取路径分别设置在DRAM阵列中。 通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。 由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高 高速运行即使在缓存未命中。

公开(公告)号：US5731727A

公开(公告)日：1998-03-24

申请号：US527968

申请日：1995-09-14

Applicant: Hisashi Iwamoto ,  Yasuhiro Konishi

Inventor： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC: G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03K19/096 ,  H03L7/081 ,  H03K5/14 ,  H03L1/00

CPC classification number: H03L7/081 ,  H03K5/133

Abstract: A control transistor is connected in parallel with an input transistor of a bias generation circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage divider resistors to be applied to the gate of the control transistor. Reduction in the power supply potential Vcc causes reduction in a current Ib flowing to the control transistor, and a current Ic=Ia+Ib flowing to a delay time variable element. When the power supply potential Vcc is reduced, the factor of a delay time period of delay time variable elements becoming shorter due to a smaller amplitude of a clock signal is canceled with the factor of the delay time period of the delay time variable elements become longer due to a smaller current Ic flowing thereto. Therefore, variation in the delay time period can be suppressed to a low level.

Abstract translation: 控制晶体管与电压控制延迟电路中的偏置产生电路的输入晶体管并联连接。 电源电位Vcc由施加到控制晶体管的栅极的分压电阻器分压。 电源电位Vcc的降低导致流向控制晶体管的电流Ib的减少，流入延迟时间可变元件的电流Ic = Ia + Ib。 当电源电位Vcc减小时，延迟时间可变元件由于时钟信号的较小振幅而变短的延迟时间的因子被延迟时间可变元件的延迟时间的因数变得更长 由于流过其的较小的电流Ic。 因此，可以将延迟时间段的变化抑制到低水平。

公开(公告)号：US5652723A

公开(公告)日：1997-07-29

申请号：US869917

申请日：1992-04-15

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

Abstract translation: 半导体存储器件包括DRAM，SRAM和设置在SRAM和DRAM之间的双向传输门电路。 SRAM阵列包括多组字线。 在SRAM阵列的每行中提供每组，并且每组中的每个字线连接到相关行的不同组的存储单元。 SRAM的地址信号和DRAM的地址信号分别应用于地址缓冲器。 半导体存储器件还包括用于实现突发模式和睡眠模式的附加功能控制电路。 从DRAM到SRAM的数据传输路径以及从SRAM到DRAM的数据传输路径分别设置在双向传输门电路中。 数据写入路径和数据读取路径分别设置在DRAM阵列中。 通过上述结构，在睡眠模式中停止缓冲电路的动作，降低功耗。 由于数据写入路径和数据读取路径分别设置在DRAM阵列中，所以可以以非多路复用的方式应用DRAM阵列的地址，从而数据可以从DRAM阵列以高速传输到SRAM阵列，使得能够高 高速运行即使在缓存未命中。

公开(公告)号：US5592434A

公开(公告)日：1997-01-07

申请号：US548285

申请日：1995-10-25

Applicant: Hisashi Iwamoto ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yasumitsu Murai

Inventor： Hisashi Iwamoto ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yasumitsu Murai

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C7/00

CPC classification number: G11C7/1048 ,  G11C7/1072

Abstract: To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.

Abstract translation: 对于一个存储器阵列，两个系统中的全局信号输入/输出线对，用于以时钟周期交替地将全局IO线对连接到写缓冲器组的开关，以及用于将全局IO线对连接到等于 提供了基于时钟周期的交替电路。 在一个时钟周期内，可以并行执行通过一个全局IO线对写入数据和对另一个全局IO线对进行均衡。 因此，可以高频地容易地写入数据。

公开(公告)号：US5587950A

公开(公告)日：1996-12-24

申请号：US461907

申请日：1995-06-05

Applicant: Seiji Sawada ,  Yasuhiro Konishi

Inventor： Seiji Sawada ,  Yasuhiro Konishi

IPC: G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/40 ,  G11C7/00

CPC classification number: G11C29/40 ,  G11C29/26

Abstract: In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

公开(公告)号：US5559750A

公开(公告)日：1996-09-24

申请号：US465472

申请日：1995-06-05

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5471430A

公开(公告)日：1995-11-28

申请号：US245784

申请日：1994-05-19

Applicant: Seiji Sawada ,  Yasuhiro Konishi

Inventor： Seiji Sawada ,  Yasuhiro Konishi

IPC: G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/02 ,  G11C29/08 ,  G11C11/34

CPC classification number: G11C29/02 ,  G11C11/406

Abstract: A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory array in accordance with an automatic refresh detection signal and the refresh address, an inactivation circuit for inactivating the refresh execution unit after a lapse of a prescribed time in accordance with the automatic refresh detection signal, a counter check mode detection circuit for bringing the inactivation circuit into an inoperable state in accordance with a counter check mode command, and a second inactivation circuit for inactivating the refresh execution unit in accordance with a precharge detection signal generated in response to a precharge command. Thus synchronous semiconductor memory device with an operation mode which can test the function of an internal refresh address counter is provided.

Abstract translation: 同步半导体存储器件包括自动刷新检测电路，用于检测根据自动刷新命令指定自动刷新模式，用于产生刷新地址的地址计数器，用于根据存储器阵列刷新存储器阵列的刷新执行单元 自动刷新检测信号和刷新地址，用于根据自动刷新检测信号在经过规定时间之后使刷新执行单元失活的灭活电路，用于使灭活电路处于不可操作状态的计数器检查模式检测电路 根据计数器检查模式命令，以及第二失活电路，用于根据预充电命令产生的预充电检测信号，使刷新执行单元失效。 因此，提供了具有可以测试内部刷新地址计数器的功能的操作模式的同步半导体存储器件。

公开(公告)号：US5359215A

公开(公告)日：1994-10-25

申请号：US795865

申请日：1991-11-22

Applicant: Yasuhiro Konishi

Inventor： Yasuhiro Konishi

IPC: G11C11/402 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10808

Abstract: A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

Abstract translation: DRAM包括在P型半导体衬底的主表面上形成的N型阱，形成在P型半导体衬底的主表面上的N型杂质区，形成在N型杂质区中的N型杂质区 型是存储电容器的存储节点，以及用于连接P型杂质区域和N型杂质区域的多晶硅层。 N型杂质层，P型杂质层和多晶硅层构成存储电容器的存储节点，并且从衬底流到N型杂质层的少数载流子的电子与从 N型阱到P型杂质层。

公开(公告)号：US5270977A

公开(公告)日：1993-12-14

申请号：US751934

申请日：1991-09-03

Applicant: Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

Inventor： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

IPC: G01R31/28 ,  G11C7/00 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: G11C11/4072 ,  G11C11/46 ,  G11C29/46

Abstract: Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.

Abstract translation: 公开了一种包括能够在短时间内测试多个存储单元是否有故障的测试模式操作的DRAM。 DRAM包括上电检测信号发生器，上电复位信号发生器和测试模式指令信号发生器。 上电检测信号发生器检测电源电压的应用并产生上电检测信号。 上电复位信号发生器由上电复位信号复位，至少在复位后施加一次外部和上升沿和R信号并产生上电复位信号。 测试模式指令信号发生器检测内部RAS信号，内部CAS信号和上电复位后施加的内部W信号的逻辑状态，并产生测试模式指令信号。