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    Semiconductor memory device for simple cache system
    81.
    发明授权
    Semiconductor memory device for simple cache system 失效
    半导体存储器件，用于简单缓存系统

    公开(公告)号：US5226147A

    公开(公告)日：1993-07-06

    申请号：US564657

    申请日：1990-08-09

    Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    IPC: G06F12/08 ,  G11C7/10

    CPC classification number: G06F12/0893 ,  G11C7/1021

    Abstract: A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

    Abstract translation: 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

    Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers
    82.
    发明授权
    Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers 失效
    包括交叉点和多个互连层的半导体存储器件的位线结构

    公开(公告)号：US5214601A

    公开(公告)日：1993-05-25

    申请号：US876690

    申请日：1992-04-28

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure includes a cross portion in at least one portion of each bit line pair so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N (N being an integer), although advantages of the invention may be obtained with division of the bit lines into 3N, and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. In a preferred embodiment, the cross parts are provided in regions for forming restore circuits or sense amplifiers. In a further embodiment, a dummy word line for selecting dummy cells for providing a reference potential is selected according to the position of a selected word line.

    Abstract translation: 折叠位线结构的半导体存储器件包括每个位线对的至少一部分中的交叉部分，使得与相邻位线对的耦合电容值相对于成对的位线彼此相等。 优选地，各位线对被均等地划分为4N（N是整数），尽管可以通过将位线划分为3N来获得本发明的优点，并且在分割点处提供交叉部分，使得位线对 将相同分割点处的交叉部分布置在交替的位线对上。 在优选实施例中，交叉部分设置在用于形成恢复电路或感测放大器的区域中。 在另一实施例中，根据所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

    Data descrambling in semiconductor memory device
    83.
    发明授权
    Data descrambling in semiconductor memory device 失效
    半导体存储器件中的数据解扰

    公开(公告)号：US5136543A

    公开(公告)日：1992-08-04

    申请号：US741208

    申请日：1991-07-31

    Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Kazutami Arimoto ,  Masaki Tsukude ,  Tsukasa Oishi

    Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Kazutami Arimoto ,  Masaki Tsukude ,  Tsukasa Oishi

    IPC: G11C7/10

    CPC classification number: G11C7/1006

    Abstract: A semiconductor memory device comprises a plurality of bit line pairs and an input/output line pair. Each bit line pair comprises first and second bit lines supplied with complementary data, and the input/output line pair comprises first and second input/output lines supplied with complementary data. A switching circuit is provided on each bit line pair. Each switching circuit, in response to a control signal according to an address signal, respectively couples the first and the second bit lines to the first and the second input/output lines, or inversely, respectively couples the first and the second bit lines to the second and the first input/output lines.

    Abstract translation: 半导体存储器件包括多个位线对和一个输入/输出线对。 每个位线对包括提供有互补数据的第一和第二位线，并且输入/输出线对包括提供有互补数据的第一和第二输入/输出线。 在每个位线对上提供开关电路。 每个开关电路响应于根据地址信号的控制信号分别将第一和第二位线耦合到第一和第二输入/输出线，或者相反地将第一和第二位线耦合到 第二个和第一个输入/输出线。

    Semiconductor memory device with cache memory addressable by block within each column
    84.
    发明授权
    Semiconductor memory device with cache memory addressable by block within each column 失效
    具有高速缓存存储器的半导体存储器件可在每列内通过块寻址

    公开(公告)号：US4926385A

    公开(公告)日：1990-05-15

    申请号：US228589

    申请日：1988-08-05

    Applicant: Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura ,  Yoshio Matsuda

    Inventor： Kazuyasu Fujishima ,  Hideto Hidaka ,  Mikio Asakura ,  Yoshio Matsuda

    IPC: G11C11/401 ,  G06F12/08 ,  G11C7/10 ,  G11C8/12 ,  G11C11/41

    CPC classification number: G11C7/103 ,  G06F12/0893 ,  G11C8/12

    Abstract: A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting circuitry selects one of the word lines responsive to a row address and reads out to each of the bit lines information stored in the memory cell associated with the selected word line. A plurality of sense amplifiers are associated with corresponding rows of the memory for detecting and amplifying the information stored in respective memory cells. A first column selector circuit selects the sense amplifiers corresponding to a column address when the column address is applied and reads information held in the sense amplifier. Blocks are formed by dividing the memory cell array into groups of bit lines, each of the groups comprising a predetermined number of bit lines with block information transferred simultaneously from corresponding ones of the groups of bit lines of a selected block when the column address corresponding to the selected block is applied. Data registers hold information of an associated block. A second column selector reads data corresponding to the column address from the data register when the column address is applied.

    Abstract translation: 半导体存储器包括具有多个位线的存储单元阵列和与位线相交的多个字线。 多个存储单元分别布置在位线和字线的交点处。 字线选择电路响应于行地址选择一个字线，并读出存储在与所选字线相关联的存储单元中的每一个位线信息。 多个读出放大器与存储器的相应行相关联，用于检测和放大存储在相应存储单元中的信息。 当应用列地址时，第一列选择器电路选择对应于列地址的读出放大器，并读取保持在读出放大器中的信息。 通过将存储单元阵列划分成位线组来形成块，每个组包括预定数量的位线，其中块信息同时从对应于所选块的位线的位线的相应位组传送 应用所选的块。 数据寄存器保存相关块的信息。 当应用列地址时，第二列选择器从数据寄存器读取与列地址对应的数据。

    Semiconductor memory device with active pull up
    86.
    发明授权
    Semiconductor memory device with active pull up 失效
    具有主动上拉功能的半导体存储器件

    公开(公告)号：US4809230A

    公开(公告)日：1989-02-28

    申请号：US938065

    申请日：1986-12-04

    Applicant: Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

    Inventor： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

    IPC: G11C11/407 ,  G11C11/34 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/00 ,  G11C7/00 ,  G11C11/40

    CPC classification number: G11C11/4076 ,  G11C11/4094

    Abstract: A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

    Abstract translation: MOS动态型RAM包括存储单元（10），虚设单元（11），位线对（BL，＆amp; B和B），字线（WL），虚拟字线（DWL）和读出放大器（12）。 在非有效周期中，每对位线（BL，＆amp; B和B）的电位在电源电位VCC的1/2处被预充电。 每个读出放大器（12）在非活动周期之后的有效周期中工作，而每个有源上拉电路（13）将该对位线中较高一级的电位上拉至VCC。 该活动周期由内部RAS内部信号定义，该内部RAS内部信号由NAND电路（27）响应于通过延迟电路（20）延迟外部＆upbar＆R信号而获得的外部＆upbar＆R信号和＆upbar＆R信号产生的内部RAS内部信号， 并且具有通过将外部＆upbar＆R信号的后沿延迟预定周期而获得的后沿。

    Dummy word line driving circuit for a MOS dynamic RAM
    87.
    发明授权
    Dummy word line driving circuit for a MOS dynamic RAM 失效
    用于MOS动态RAM的虚拟字线驱动电路

    公开(公告)号：US4757476A

    公开(公告)日：1988-07-12

    申请号：US876912

    申请日：1986-06-20

    Applicant: Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

    Inventor： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

    IPC: G11C11/401 ,  G11C7/14 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4099 ,  G11C7/02

    CPC classification number: G11C7/14 ,  G11C11/4099

    Abstract: A dummy word line driving circuit for a MOS dynamic RAM comprises a dummy word line controller connected to each end of a pair of dummy word lines. A sub-decode signal which is opposite to the one inputted to a dummy word driver and a dummy set signal for writing a bit line information into a not-selected dummy cell are inputted to the dummy word line controller. Means for applying a dummy equalizing signal is connected to two full-sized dummy cells, for equalizing the two before the dummy word line is driven. The two full-sized dummy cells are equalized by the signal, resulting in a charge amount, which is to be a reference value, of a half of a full-sized memory cell.

    Abstract translation: 用于MOS动态RAM的虚拟字线驱动电路包括连接到一对虚拟字线的每一端的虚拟字线控制器。 将与输入到虚拟字驱动器的子解码信号相反的子解码信号和用于将位线信息写入未选择的虚拟单元的伪设置信号被输入到虚拟字线控制器。 用于应用虚拟均衡信号的装置连接到两个全尺寸的虚拟小区，用于在虚拟字线被驱动之前均衡两者。 两个全尺寸虚拟单元被信号相等，导致作为参考值的充电量为全尺寸存储单元的一半。

    Driving circuit for a shared sense amplifier
    90.
    发明授权
    Driving circuit for a shared sense amplifier 失效
    用于共享读出放大器的驱动电路

    公开(公告)号：US4710901A

    公开(公告)日：1987-12-01

    申请号：US767193

    申请日：1985-08-19

    Applicant: Masaki Kumanoya ,  Kazuyasu Fujishima ,  Katsumi Dosaka

    Inventor： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Katsumi Dosaka

    IPC: G11C11/409 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

    CPC classification number: G11C7/06 ,  G11C7/18 ,  G11C7/22

    Abstract: When any one of memory cells (MC.sub.1R, MC.sub.NR and MC.sub.1L, MC.sub.NL) connected with respective bit lines (3.sub.R, 4.sub.R and 3.sub.L, 4.sub.L) is addressed, the gate potential of a transfer transistor group (7.sub.R, 8.sub.R or 7.sub.L, 8.sub.L) connected with the bit lines on the non-selected side is clamped at bit line precharge voltage, whereby the said transfer transistor group (7.sub.R, 8.sub.R or 7.sub.L, 7.sub.L) is turned off. Thus, the bit lines on the non-selected side are cut off at a high speed from a sense amplifier.

    Abstract translation: 当与各个位线（3R，4R和3L，4L）连接的存储单元（MC1R，MCNR和MC1L，MCNL）中的任何一个被寻址时，传输晶体管组（7R，8R或7L，8L）的栅极电位连接 其中非选择侧的位线被钳位在位线预充电电压，由此所述转移晶体管组（7R，8R或7L，7L）截止。 因此，非选择侧的位线从读出放大器以高速切断。

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