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公开(公告)号：US3789360A
公开(公告)日：1974-01-29
申请号：US3789360D
申请日：1972-10-13
Applicant: HARRIS INTERTYPE CORP
CPC classification number: H04L1/0054
Abstract: A decoder for correcting and decoding convolutional data. Decoding of each digit of sequentially received data is postponed until a plurality of subsequent digits have been received. A message digit is then decoded by comparing the received sequence of data with a limited number of possible messages. The possible message which correlates best with the sequence of convolutional data that was received is temporarily assumed to be the correct sequence for purposes of decoding only the first message digit or perhaps the first few message digits of the data sequence currently being considered. The limited number of possible messages to be compared with the received data are selected at each branch interval by choosing one sequence terminating in each data state. During decoding, the possible messages are represented as sequences of branch transitions among a predetermined number of data states. The transitions among states are traced step by step through the possible message sequences to ascertain the data state of a survivor sequence at the decoding depth. The data state of the highest correlated survivor path is then interpreted into a decoded message bit.
Abstract translation: 用于校正和解码卷积数据的解码器。 顺序接收数据的每个数字的解码被推迟直到接收到多个后续数字。 然后通过将接收到的数据序列与有限数量的可能消息进行比较来解码消息数字。 暂时假定与接收到的卷积数据序列最相关的可能消息是正确的序列，用于仅解码当前正在考虑的数据序列的第一消息数字或最初几个消息数字。 通过选择在每个数据状态终止的一个序列，在每个分支间隔选择与接收数据进行比较的可能消息的有限数量。 在解码期间，可能的消息被表示为预定数量的数据状态之间的分支转换序列。 通过可能的消息序列逐步跟踪状态之间的转换，以确定解码深度处的幸存者序列的数据状态。 然后将最高相关幸存路径的数据状态解释为解码消息位。
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公开(公告)号：US3786439A
公开(公告)日：1974-01-15
申请号：US3786439D
申请日：1972-12-26
Applicant: IBM
Inventor： MC DONALD E , PATEL A
CPC classification number: G11B20/1833
Abstract: Error detection is enhanced by using multiple independent error codes combined with nonlinear changes in the data field as applied to different error codes. Such nonlinear permutations increase the probability of detecting errors thereby maximizing the utilization of check bit redundancies. In a magnetic tape subsystem, error detection and correction can be enhanced by scrambling track-to-error code relationships between a plurality of independent codes. Tracks with the highest probability of errors, i.e., the outside tracks on a 1/2 inch tape, for example, are connected to nonadjacent inputs of error correction code apparatus. Additionally, the input-to-track relationship of various code apparatus can be scrambled, either permanently or during a tape transducing operation. The above permutations provide best advantage with selected error correction codes and systems having identifiable probability of error patterns.
Abstract translation: 通过使用多个独立的错误代码结合应用于不同错误代码的数据字段中的非线性变化来增强错误检测。 这种非线性置换增加了检测错误的可能性，从而最大化了校验位冗余的利用率。 在磁带子系统中，可以通过对多个独立代码之间的跟踪到错误代码关系进行加扰来增强错误检测和校正。 具有最高错误概率的轨道，例如1/2英寸磁带上的外部磁道，连接到纠错码装置的不相邻的输入端。 此外，可以永久地或在磁带传输操作期间扰乱各种代码设备的输入到轨道的关系。 上述排列为选择的纠错码和具有可识别的错误模式概率的系统提供了最佳的优点。
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公开(公告)号：US3665396A
公开(公告)日：1972-05-23
申请号：US3665396D
申请日：1968-10-11
Applicant: CODEX CORP
Inventor： FORNEY GEORGE DAVID JR
CPC classification number: H03M13/39 , H04L1/0054
Abstract: An improved error-correcting decoder for convolutional codes, of the sequential decoding type, is described. By restriction of received digit quantization to hard decisions, the number of alternatives in a single decoding search move is made sufficiently small that an entire move can be completed in one cycle of a synchronous clock. An efficient organization of the decoder memory is disclosed in which the decoder logic circuitry operates on a small, fast memory, while a larger, slower bulk buffer memory interfaces with the channel, stores data, and exchanges bits with the small fast memory on demand. The bulk memory contains variable amounts of decoded and undecoded data, which together comprise a constant capacity. A new buffer memory employing untapped shift registers is described. Use of a syndrome-forming circuit to preprocess the data is disclosed. An automatic resynchronization method in which a number of stored syndrome bits are set to 0 is presented. These features in combination are employed to produce efficient communication at high data rates over satellite channels.
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公开(公告)号：US3641494A
公开(公告)日：1972-02-08
申请号：US3641494D
申请日：1970-02-12
Applicant: INT STANDARD ELECTRIC CORP
Inventor： PERRAULT JEAN , SALLE ADELIN E G
Abstract: A bidirectional data transmission system for transmitting information between two terminal stations incorporating in each terminal station an arrangement for checking the received data and providing error correction when errors are detected in the received data. Each of the terminals include a memory for storing the m last words transmitted from that terminal. When an error is detected in one terminal, the transfer of received data to a data processor is blocked and a repetition request word is generated and transmitted to the other terminal. The other terminal detects the presence of the repetition request word in the received data and transmits a repetition start word and the last m data words stored in the memory to said one terminal to accomplish the error correction.
Abstract translation: 一种双向数据传输系统，用于在包含在每个终端站中的两个终端站之间传输信息，用于检查所接收的数据并在接收的数据中检测到错误时提供纠错。 每个终端包括用于存储从该终端发送的最后一个字的存储器。 当在一个终端中检测到错误时，将接收到的数据传送到数据处理器被阻塞，并产生一个重复请求字并发送给另一个终端。 另一终端检测接收到的数据中的重复请求字的存在，并将存储在存储器中的重复开始字和最后m个数据字发送到所述一个终端，以完成纠错。
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75.发明授权Error correcting decoder utilizing estimator functions and decision circuit for bit-by-bit decoding 失效错误修正解码器利用估算器功能和决策电路进行位位解码
公开(公告)号：US3639901A
公开(公告)日：1972-02-01
申请号：US3639901D
申请日：1969-06-10
Applicant: GEN ELECTRIC
Inventor： MITCHELL MICHAEL E
CPC classification number: H04L1/0057 , H03M13/43
Abstract: An error-correcting decoder circuit is disclosed, for decoding redundantly coded digital signals. The disclosed circuit includes a plurality of modulo 2 adders for generating estimator function bits from selected bits of a received code word, and a decision circuit that generates an output bit in accordance with the majority of the estimator functions if a majority decision is possible, and which substitutes the appropriate received bit in place of the undefined majority decision output that arises in the event of a ''''tie'''' between the estimator functions (i.e., when half of the estimator functions are ''''1'''' and the other half are ''''0'''').
Abstract translation: 公开了一种用于解码冗余编码的数字信号的纠错解码器电路。 所公开的电路包括多个模2加法器，用于从所接收的代码字的选定位产生估计器函数位;以及判定电路，如果多数决定是可能的，则根据估计器函数的大部分生成输出位;以及 其代替适当的接收位代替在估计器函数之间“（”估计器函数的一半为“1”而另一半为“0”）的情况下出现的未定义的多数决定输出。 。
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Patent Agency Ranking
公开(公告)号：US3593009A
公开(公告)日：1971-07-13
申请号：US3593009D
申请日：1969-09-22
Applicant: ZENTRONIK KARL MARX STADT VEB
Inventor： UNTERSCHUTZ HANS-GERD , KUTSCHBACH ERNST
CPC classification number: G06F11/104
Abstract: The device comprises groups of diodes for coding respective digits of the number under test, a first counter, an adjustment pulse generator connected between the groups of diodes and the first counter to set the same to a complementary number, resetting pulse generator means, second and third counters, AND and OR gate members, a flip-flop circuit controlled by the input of the device, means for inverting the pulses from the resetting pulse generator and alternately feeding the same for the addition in the second and third counter to provide a constant residual number.
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公开(公告)号：US3582878A
公开(公告)日：1971-06-01
申请号：US3582878D
申请日：1969-01-08
Applicant: IBM , ROBERT T CHIEN
Inventor： BOSSEN DOUGLAS C , CHIEN ROBERT T , HSIAO MU-YUE , SELLERS FREDERICK F JR
CPC classification number: H04L1/0057 , H03M13/19 , H04L1/0041
Abstract: The error correcting system is capable of correcting multiple random errors in data messages of k m2 data bits where m is an integer. The message is encoded by adding 2m check bits for each additional error correcting capability. The encoded message after data transfer and storage is decoded by parity checking and threshold logic decision circuits. The parity checking circuits are constructed in modular form. Each additional module adds a further error correcting capability. The outputs from each module form inputs to the threshold logic decision circuit where the error correction is made. Detection of an additional error can be simply achieved by an overall parity circuit.
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公开(公告)号：US3579185A
公开(公告)日：1971-05-18
申请号：US3579185D
申请日：1968-09-20
Applicant: IBM
Inventor： SPRUTH WILHELM
CPC classification number: G06F11/10 , H04L1/0045 , H04L1/0063
Abstract: The accuracy of a data transfer operation, particularly one which involves loading a micro program into an alterable control storage device for use in a data processing system, is verified by deriving a check number from the transferred data and comparing the desired check number with a predetermined check number known to be correct. A variety of concepts may be used to obtain the derived check number such as successive logical Exclusive OR operations on transferred blocks of data or selected portions of the blocks.
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公开(公告)号：US3562711A
公开(公告)日：1971-02-09
申请号：US3562711D
申请日：1968-07-16
Applicant: IBM
Inventor： DAVIS ROBERT H , BOUDREAU PAUL E , HARRIS JERRY S
CPC classification number: H04L1/0057
Abstract: A DEVICE FOR DETECTING CIRCUIT MALFUNCTIONS IN CERTAIN LINEAR SWITCHING CIRCUITS OPERATED IN SUCCESSIVE TIME PERIODS WHICH HAS A FIRST CIRCUIT FOR GENERATING A PREDICTED PARITY SIGNAL FOR EACH SUCCESSIVE TIME PERIOD, A PARITY CHECK CIRCUIT FOR GENERATING A SIGNAL INDICATIVE OF ACTUAL PARITY DURING EACH SUCCESSIVE TIME PERIOD, AND A COMPARATOR FOR COMPARING THE SIGNALS REPRESENTING THE PREDICTED PARITY AND THE ACTUAL PARITY DURING EACH SUCCESSIVE TIME PERIOD, THEREBY TO INDICATE ANY CIRCUIT MALFUNCTION DURING EACH SUCH SUCCESSIVE TIME PERIOD.
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公开(公告)号：US3544963A
公开(公告)日：1970-12-01
申请号：US3544963D
申请日：1968-12-27
Applicant: BELL TELEPHONE LABOR INC
Inventor： TONG SHIH Y
CPC classification number: H03M13/17
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