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    Augmented digital-error-correcting decoder
    2.
    发明授权
    Augmented digital-error-correcting decoder 失效
    已解决的数字错误修正解码器

    公开(公告)号：US3609682A

    公开(公告)日：1971-09-28

    申请号：US3609682D

    申请日：1969-07-16

    Applicant: GEN ELECTRIC

    Inventor： MITCHELL MICHAEL E

    IPC: G06F11/00 ,  H03M13/45 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

    CPC classification number: H04L1/0057 ,  H03M13/45 ,  H03M13/458

    Abstract: An error correcting decoder circuit for decoding redundantly coded received digital signals. Estimator bits are generated from selected bits of a received code word, and estimator reliability signals are generated in accordance with word-bit error probability signals derived from the received analog signal amplitudes associated with the same selected bits of the code word as are used for generating the estimator bits. The estimator reliability signals are used as a basis for weighting the bipolar estimator bit voltages, by increasing or decreasing their absolute values, whereby the more reliable estimator bits are given greater weights at the input of a threshold decision circuit. The threshold decision circuit generates an output bit in accordance with the arithmetic sum of the weighted estimator bit voltages, except that it substitutes the appropriate received bit in place of the unreliable threshold decision that arises in the event that the sum is small in magnitude. Control circuitry is provided for causing repetitive shifting of the word bits in a first shift register and of word-bit error probability signals in a second shift register, for performing step-by-step decoding of a received word with the aid of the received signal reliability indications. The invention thus provides a means of augmenting the digital error correction capability of decoders through the use of auxiliary outputs from the receiver which indicate the received signal quality.

    Random error correcting coding and decoding system having inversion tolerance and double code capability
    4.
    发明授权
    Random error correcting coding and decoding system having inversion tolerance and double code capability 失效
    随机错误校正编码和解码系统具有反转容忍度和双重代码能力

    公开(公告)号：US3587042A

    公开(公告)日：1971-06-22

    申请号：US3587042D

    申请日：1969-07-03

    Applicant: GEN ELECTRIC

    Inventor： MITCHELL MICHAEL E

    IPC: H03M13/43 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

    CPC classification number: H04L1/0057 ,  H03M13/43

    Abstract: An improved error correcting coding and decoding system for reliable data transmission. During a first subcycle of decoder operation, estimator logic circuitry generates successive sets of estimator function bits from selected bits of a received code word, and a decision circuit generates successive test bits in accordance with a bit derived from a number of the estimator function bits. A modulo 2 adder compares the successive test bits with the corresponding received bits, and a counter circuit counts the number of disagreements. A disagreement count exceeding a predetermined number indicates that the received code word has become inverted, and circuitry then functions to correct for the inversion by either complementing the received code word before the second decoding subcycle or by complementing the output of the decoding decision circuit during the second subcycle. During the second decoding subcycle, the decision circuit generates successive decoded bits as determined from a majority of the estimator function bits and also from a code word bit if desired. In the event of a ''''tie'''' among the estimator bits, the indeterminate majority decision bit is replaced with the corresponding received bit. The encoding and decoding system may be used either for inversion tolerant coding and decoding of an appropriate code (such as the (21,11) code) or for noninversion tolerant coding and decoding of a related type of code (such as the (21,12) code).

    Error correcting decoder utilizing estimator functions and decision circuit for bit-by-bit decoding
    5.
    发明授权
    Error correcting decoder utilizing estimator functions and decision circuit for bit-by-bit decoding 失效
    错误修正解码器利用估算器功能和决策电路进行位位解码

    公开(公告)号：US3639901A

    公开(公告)日：1972-02-01

    申请号：US3639901D

    申请日：1969-06-10

    Applicant: GEN ELECTRIC

    Inventor： MITCHELL MICHAEL E

    IPC: H03M13/43 ,  H04L1/00 ,  H04L1/10 ,  H03K19/42

    CPC classification number: H04L1/0057 ,  H03M13/43

    Abstract: An error-correcting decoder circuit is disclosed, for decoding redundantly coded digital signals. The disclosed circuit includes a plurality of modulo 2 adders for generating estimator function bits from selected bits of a received code word, and a decision circuit that generates an output bit in accordance with the majority of the estimator functions if a majority decision is possible, and which substitutes the appropriate received bit in place of the undefined majority decision output that arises in the event of a ''''tie'''' between the estimator functions (i.e., when half of the estimator functions are ''''1'''' and the other half are ''''0'''').

    Abstract translation: 公开了一种用于解码冗余编码的数字信号的纠错解码器电路。 所公开的电路包括多个模2加法器，用于从所接收的代码字的选定位产生估计器函数位;以及判定电路，如果多数决定是可能的，则根据估计器函数的大部分生成输出位;以及 其代替适当的接收位代替在估计器函数之间“（”估计器函数的一半为“1”而另一半为“0”）的情况下出现的未定义的多数决定输出。 。

    Inversion-tolerant random error correcting digital data transmission system
    6.
    发明授权
    Inversion-tolerant random error correcting digital data transmission system 失效
    反向容忍随机错误校正数字数据传输系统

    公开(公告)号：US3577186A

    公开(公告)日：1971-05-04

    申请号：US3577186D

    申请日：1969-05-28

    Applicant: GEN ELECTRIC

    Inventor： MITCHELL MICHAEL E

    IPC: H03M13/43 ,  H04L1/00 ,  H04L27/06 ,  G08C25/00 ,  H04L7/00

    CPC classification number: H04L1/0057 ,  H03M13/43 ,  H04L27/066

    Abstract: A digital data transmission system is disclosed which decodes received error correction coded digital signals properly, irrespective of whether or not the polarities of these signals have become inverted during transmission or reception. The system thus permits a 180* phase ambiguity in the reinsertion of a regenerated suppressed carrier or subcarrier signal in the receiver, thereby simplifying the receiver in addition to correcting errors to improve the reliability of data transmission. The disclosed decoder circuitry includes a plurality of modulo 2 adder circuits for generating a plurality of estimators each of which is the mod 2 sum of an even number of the received digits. These estimators are fed to a threshold decision circuit which provides a serial readout of the decoded digits. The threshold decision circuit may consist of a simple majority decision circuit or a multiple input threshold circuit with either equal or unequal weighting factors on its input estimators.

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