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    Majority decision logic circuit
    3.
    发明授权
    Majority decision logic circuit 失效
    多数决策逻辑电路

    公开(公告)号：US4091293A

    公开(公告)日：1978-05-23

    申请号：US750884

    申请日：1976-12-15

    申请人： Hisashige Ando

    发明人： Hisashige Ando

    IPC分类号： H03K19/23 ,  H03K19/08 ,  H03K19/42

    CPC分类号： H03K19/23

    摘要： A majority decision logic circuit has an odd number of elementary input signal circuits connected in parallel with a power source, each of the elementary input signal circuits being composed of a pair of P- and N-channel MOS transistors, the drains of the MOS transistors being interconnected to form an output terminal at the connection point and the gates being interconnected to form an input terminal at the connection point, all the output terminals of the elementary input signal circuits being connected together to form the output terminal of the majority decision logic circuit. A majority decision logic circuit has, in addition to the odd number of elementary input signal circuits, a plurality of logic circuits having their output terminals respectively connected to the input terminal of the elementary input signal circuits. A majority decision logic circuit comprises the elementary input signal circuits, the logic circuits and switching circuits, whereby the majority of outputs of a selected odd number of input signal circuits is decided. The abovesaid circuits can be formed with MOS transistors only, and are easily fabricated as an integrated circuit.

    摘要翻译： 多数决定逻辑电路具有与电源并联连接的奇数个基本输入信号电路，每个基本输入信号电路由一对P-沟道MOS晶体管和N沟道MOS晶体管构成，MOS晶体管的漏极 互连以在连接点处形成输出端子，并且门互连以在连接点处形成输入端子，基本输入信号电路的所有输出端子连接在一起以形成多数决定逻辑电路的输出端子 。 除了奇数个基本输入信号电路之外，多数决定逻辑电路具有分别连接到基本输入信号电路的输入端的多个逻辑电路。 多数决定逻辑电路包括基本输入信号电路，逻辑电路和开关电路，从而确定所选奇数个输入信号电路的大部分输出。 上述电路可以仅由MOS晶体管形成，并且容易地制造为集成电路。

    Threshold gate circuits employing field-effect transistors
    4.
    发明授权
    Threshold gate circuits employing field-effect transistors 失效
    采用现场效应晶体管的栅极电路

    公开(公告)号：US3715603A

    公开(公告)日：1973-02-06

    申请号：US3715603D

    申请日：1971-10-28

    申请人： RCA CORP

    发明人： LERCH J

    IPC分类号： H03K19/0948 ,  H03K19/23 ,  H03K19/42

    CPC分类号： H03K19/0948

    摘要： A threshold gate comprising a plurality of complementarysymmetry, field-effect transistor inverters, each inverter receiving at its common gate connection a different input signal and each connected at its output terminal to a common circuit output terminal. The gate may have inputs all of the same weight or, with appropriately chosen values of transistor conduction channel impedance or parallel connected inverters, may have inputs of different weight.

    摘要翻译： 一种阈值门，包括多个互补对称的场效应晶体管反相器，每个反相器在其公共栅极连接处接收不同的输入信号，并且每个反相器在其输出端连接到公共电路输出端。 栅极可以具有相同重量的输入，或者具有适当选择的晶体管导通通道阻抗值或并联逆变器的值可能具有不同重量的输入。

    Threshold logic for integrated full adder and the like
    5.
    发明授权
    Threshold logic for integrated full adder and the like 失效
    集成的全面添加和类似的THRESHOLD逻辑

    公开(公告)号：US3609329A

    公开(公告)日：1971-09-28

    申请号：US3609329D

    申请日：1969-05-05

    申请人： SHELL OIL CO

    发明人： MARTIN HAROLD M

    IPC分类号： G06F7/50 ,  G06F7/501 ,  H03K19/096 ,  H03K19/08 ,  H03K19/42

    CPC分类号： G06F7/501 ,  G06F2207/4818 ,  H03K19/096

    摘要： Threshold logic functions are carried out by the use of an insulated-gate field effect transistor (IGFET) connected as a sampler transistor in series with a not-clock input and a parallel combination of several data input IGFET''s. The sampler transistor and the data input transistor combination form a voltage divider whose center tap is connected to the input of an IGFET inverter operated from a clock input. By using data input IGFET''s with different ''''on'''' resistances, the data inputs can be selectively weighted, and a full adder circuit can be constructed with only 15 components, all of which are IGFET''s, and all of which can be manufactured on a single chip.

    Optically isolated solid state relay
    7.
    发明授权
    Optically isolated solid state relay 失效
    光电隔离固态继电器

    公开(公告)号：US4408131A

    公开(公告)日：1983-10-04

    申请号：US303811

    申请日：1981-09-21

    申请人： David A. Fox

    发明人： David A. Fox

    IPC分类号： H03K17/785 ,  H03K3/42 ,  H03K19/42

    CPC分类号： H03K17/785

    摘要： A solid state relay is provided with a control logic circuit which receives a low level input control signal and controls a power field effect transistor (FET) switching element by means of an optical isolator. Connecting an external power source to a function selecting input terminal causes the relay to operate as a normally open, normally closed, or latching relay. A voltage spike suppression network protects the FET from voltage spikes appearing across it.

    摘要翻译： 固态继电器具有控制逻辑电路，其接收低电平输入控制信号，并通过光隔离器控制功率场效应晶体管（FET）开关元件。 将外部电源连接到功能选择输入端子可使继电器作为常开常闭或闭锁继电器工作。 电压尖峰抑制网络保护FET免受其上出现的电压尖峰。

    Latched gating circuit
    9.
    发明授权
    Latched gating circuit 失效
    锁定加注电路

    公开(公告)号：US3737675A

    公开(公告)日：1973-06-05

    申请号：US3737675D

    申请日：1971-12-15

    申请人： LEAR SIEGLER INC

    发明人： CAMPBELL R

    IPC分类号： H03K3/2893 ,  H03K19/08 ,  H03K17/30 ,  H03K3/295 ,  H03K19/42

    CPC分类号： H03K19/0813 ,  H03K3/2893

    摘要： A latched gating circuit that is characterized by remaining in an ''''enabled'''' state until removal of all inputs initially required to switch the circuit to the ''''enabled'''' state, is disclosed. The circuit includes a gating transistor which is rendered conductive in response to the application of input signals to preselected ones of the input terminals of the gating circuit. A latching transistor is connected in a feedback arrangement between the gating transistor and the input terminals to maintain the gating transistor conductive until all of the input signals are removed.

    摘要翻译： 公开了一种锁存门控电路，其特征在于保持在“使能”状态，直到将最初需要的所有输入切换到“启用”状态为止。 电路包括门控晶体管，其响应于将输入信号施加到门控电路的预选输入端而导通。 锁存晶体管连接在门控晶体管和输入端子之间的反馈装置中，以保持门控晶体管导通，直到所有输入信号被去除。

    Limited average voter circuitry
    10.
    发明授权
    Limited average voter circuitry 失效
    有限平均电话电路

    公开(公告)号：US3686493A

    公开(公告)日：1972-08-22

    申请号：US3686493D

    申请日：1970-11-13

    申请人： GEN ELECTRIC

    发明人： SCHMID HERMANN

    IPC分类号： G06G7/14 ,  H03K19/003 ,  H03K19/42

    CPC分类号： H03K19/00392 ,  G06G7/14

    摘要： Electronic computer and control circuitry providing for redundancy by use of plural parallel channels and for selection of the proper output by limiting the difference between each input signal and the output signal and selecting an output based on the average of the limited signals. A specific analog circuit embodying the concept is described.

    摘要翻译： 电子计算机和控制电路通过使用多个并行通道提供冗余并通过限制每个输入信号和输出信号之间的差异来选择适当的输出，并且基于有限信号的平均值选择输出。 描述体现该概念的特定模拟电路。