公开(公告)号：US3613077A

公开(公告)日：1971-10-12

申请号：US3613077D

申请日：1969-08-25

Applicant: CODEX CORP

Inventor： FORNEY GEORGE DAVID JR

IPC: H04L1/00 ,  G08C25/00

CPC classification number: H04L1/00

Abstract: Error correction in modems and similar sampled-data circuits that have outputs representable as outputs of a linear circuit with integer-valued impulse response when the integer-valued input sequence is subject to predetermined constraints. Integervalued tentative decisions and reliability information are formed and stored. A correction is made upon detection, on the basis of the constraints, of an error in the tentative decisions. Shown also are: an inverse linear circuit for detecting decision errors according to whether its outputs satisfy the constraints, with means to combat propagation of the error in the inverse circuit; reliability information in the form of magnitude and sign of apparent errors, especially storing only the extreme values of apparent errors in the sequence under review; constraints in form of predetermined finite range of integers and detection with an inverse circuit on basis of values falling outside of the finite range, also combating propagation by replacement of erroneous value with closest substitute satisfying the constraints; and impulse responses of the form 1 + OR - Dn, where n integer, and division of tentative decisions and memory into related groups.

公开(公告)号：US3665396A

公开(公告)日：1972-05-23

申请号：US3665396D

申请日：1968-10-11

Applicant: CODEX CORP

Inventor： FORNEY GEORGE DAVID JR

IPC: H03M13/39 ,  H04L1/00 ,  H03K13/34 ,  H04L1/10

CPC classification number: H03M13/39 ,  H04L1/0054

Abstract: An improved error-correcting decoder for convolutional codes, of the sequential decoding type, is described. By restriction of received digit quantization to hard decisions, the number of alternatives in a single decoding search move is made sufficiently small that an entire move can be completed in one cycle of a synchronous clock. An efficient organization of the decoder memory is disclosed in which the decoder logic circuitry operates on a small, fast memory, while a larger, slower bulk buffer memory interfaces with the channel, stores data, and exchanges bits with the small fast memory on demand. The bulk memory contains variable amounts of decoded and undecoded data, which together comprise a constant capacity. A new buffer memory employing untapped shift registers is described. Use of a syndrome-forming circuit to preprocess the data is disclosed. An automatic resynchronization method in which a number of stored syndrome bits are set to 0 is presented. These features in combination are employed to produce efficient communication at high data rates over satellite channels.

公开(公告)号：US3652998A

公开(公告)日：1972-03-28

申请号：US3652998D

申请日：1970-03-01

Applicant: CODEX CORP

Inventor： FORNEY GEORGE DAVID JR

IPC: G06F7/76 ,  H03M13/27 ,  G06F13/02 ,  G06F7/00

CPC classification number: G06F7/762 ,  G06F7/76 ,  H03M13/27

Abstract: Interleavers, which spread the bits in a group of length B in the input sequence so that any pair are at least N bits apart in the output sequence, in which delaying circuitry (e.g., one or more shift registers) cooperates with control circuitry to define a plurality of delay paths, each of which is of constant length, the number of such paths being equal to the period, P, of the interleaver (where 2

Abstract translation: 交织器，其在输入序列中扩展长度为B的组中的比特，使得任何对在输出序列中至少为N比特，其中延迟电路（例如，一个或多个移位寄存器）与控制电路协作来定义 多个延迟路径，每个延迟路径具有恒定长度，这些路径的数目等于交织器的周期P（其中2