公开(公告)号：US20240274695A1

公开(公告)日：2024-08-15

申请号：US18644330

申请日：2024-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Yi Tsai ,  Chi-Hsiang Chang ,  Shih-Yao Lin ,  Tzu-Chung Wang ,  Shu-Yuan Ku

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

摘要： A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.

公开(公告)号：US12046597B2

公开(公告)日：2024-07-23

申请号：US17460583

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Uei Jang ,  Shih-Yao Lin ,  Chieh-Ning Feng ,  Shu-Yuan Ku

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

摘要： A semiconductor device includes a substrate; a semiconductor fin structure disposed over the substrate, wherein the semiconductor fin structure extend along a first lateral direction; a gate structure that straddles a semiconductor fin structure, wherein the gate structure extends along a second lateral direction, the first lateral direction perpendicular to the second lateral direction; a dielectric fin structure that extends along the first lateral direction and is disposed next to the semiconductor structure fin structure; and a gate isolation structure disposed above the dielectric fin structure. The gate isolation structure contacts an upper portion of the gate structure at a first tilted interface.

公开(公告)号：US12027624B2

公开(公告)日：2024-07-02

申请号：US18066777

申请日：2022-12-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Hsiao Wen Lee ,  Li-Jung Kuo ,  Chen-Ping Chen ,  Ming-Ching Chang

IPC分类号： H01L29/76 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795

摘要： A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

公开(公告)号：US11942529B2

公开(公告)日：2024-03-26

申请号：US17834614

申请日：2022-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Hsiao Wen Lee

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/3065

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/7831 ,  H01L29/78696 ,  H01L21/3065

摘要： A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

公开(公告)号：US11928415B2

公开(公告)日：2024-03-12

申请号：US18157988

申请日：2023-01-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching Hsu ,  Shih-Yao Lin ,  Yi-Lin Chuang

IPC分类号： G06F30/398 ,  G06F30/392 ,  G06N5/04 ,  G06N20/00

CPC分类号： G06F30/398 ,  G06F30/392 ,  G06N5/04 ,  G06N20/00

摘要： A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

公开(公告)号：US11842929B2

公开(公告)日：2023-12-12

申请号：US17461184

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuei-Yu Kao ,  Shih-Yao Lin ,  Chen-Ping Chen ,  Chih-Chung Chiu ,  Chen-Yui Yang ,  Ke-Chia Tseng ,  Hsien-Chung Huang ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L21/823468 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78696

摘要： A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

公开(公告)号：US20230067425A1

公开(公告)日：2023-03-02

申请号：US17460203

申请日：2021-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chen-Ping Chen ,  Chen-Yui Yang ,  Hsiao Wen Lee ,  Ming-Ching Chang

IPC分类号： H01L21/8234 ,  H01L27/088

摘要： A semiconductor device includes a first plurality of channel layers. The first plurality of channel layers extend along a first direction. The semiconductor device includes a second plurality of channel layers. The second plurality of channel layers also extend along the first direction. The semiconductor de123329-vice includes a first dielectric fin structure that also extends along the first direction. The semiconductor device includes a first gate structure that extends along a second direction. The first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers. The first dielectric fin structure separates the first and second portions from each other. The first gate structure comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.

公开(公告)号：US20230066828A1

公开(公告)日：2023-03-02

申请号：US17460583

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Uei Jang ,  Shih-Yao Lin ,  Chieh-Ning Feng ,  Shu-Yuan Ku

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

摘要： A semiconductor device includes a substrate; a semiconductor fin structure disposed over the substrate, wherein the semiconductor fin structure extend along a first lateral direction; a gate structure that straddles a semiconductor fin structure, wherein the gate structure extends along a second lateral direction, the first lateral direction perpendicular to the second lateral direction; a dielectric fin structure that extends along the first lateral direction and is disposed next to the semiconductor structure fin structure; and a gate isolation structure disposed above the dielectric fin structure. The gate isolation structure contacts an upper portion of the gate structure at a first tilted interface.

公开(公告)号：US20230061323A1

公开(公告)日：2023-03-02

申请号：US17460198

申请日：2021-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Yi Tsai ,  Shih-Yao Lin ,  Chi-Hsiang Chang ,  Wei-Han Chen ,  Shu-Yuan Ku

IPC分类号： H01L27/088 ,  H01L21/8234

摘要： A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

公开(公告)号：US20230016605A1

公开(公告)日：2023-01-19

申请号：US17376960

申请日：2021-07-15

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Shih-Yao Lin ,  Chao-Cheng Chen ,  Chih-Han Lin ,  Chen-Ping Chen ,  Ming-Ching Chang ,  Chia-Hao Yu ,  Hsiao Wen Lee

IPC分类号： H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311

摘要： A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.