公开(公告)号：US20220215869A1

公开(公告)日：2022-07-07

申请号：US17703869

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US11309005B2

公开(公告)日：2022-04-19

申请号：US16655056

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/00 ,  G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US20210391443A1

公开(公告)日：2021-12-16

申请号：US16901881

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternately stacked, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region thereby forming an opening exposing at least one second semiconductor layer. The method also includes implanting an etch rate modifying species into the at least one second semiconductor layer though the opening thereby forming an implanted portion of the at least one second semiconductor layer. The method further includes selectively etching the implanted portion of the at least one second semiconductor layer, recessing end portions of the first semiconductor layers exposed in the opening, and forming an S/D epitaxial layer in the opening.

公开(公告)号：US20210376119A1

公开(公告)日：2021-12-02

申请号：US17200291

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

公开(公告)号：US11031418B2

公开(公告)日：2021-06-08

申请号：US16741530

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L21/762 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US20210066477A1

公开(公告)日：2021-03-04

申请号：US16931930

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain trench; laterally etching the first semiconductor layers through the source/drain trench; forming an inner spacer layer, in the source/drain trench, at least on lateral ends of the etched first semiconductor layers; forming a seeding layer on the inner spacer layer; and growing a source/drain epitaxial layer in the source/drain trench, wherein the growing of the source/drain epitaxial layer includes growing the source/drain epitaxial layer from the seeding layer.

公开(公告)号：US20200152666A1

公开(公告)日：2020-05-14

申请号：US16741530

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US20190237572A1

公开(公告)日：2019-08-01

申请号：US16376563

申请日：2019-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

公开(公告)号：US10193090B2

公开(公告)日：2019-01-29

申请号：US15627722

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Jean-Pierre Colinge ,  Ken-Ichi Goto ,  Zhiqiang Wu ,  Yu-Ming Lin

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

公开(公告)号：US10008603B2

公开(公告)日：2018-06-26

申请号：US15355844

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78654 ,  H01L29/78696

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.