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公开(公告)号：US20210158863A1
公开(公告)日：2021-05-27
申请号：US16693949
申请日：2019-11-25
发明人： Dale H. Hiscock , Debra M. Bell , Michael Kaminski , Joshua E. Alzheimer , Anthony D. Veches , James S. Rehmeyer
IPC分类号： G11C11/406 , G11C11/4074 , G11C11/409 , G11C29/00
摘要： Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory row and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.
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公开(公告)号：US11017879B1
公开(公告)日：2021-05-25
申请号：US16723532
申请日：2019-12-20
摘要： Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.
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73.发明授权公开(公告)号：US10818338B2
公开(公告)日：2020-10-27
申请号：US15930268
申请日：2020-05-12
摘要： Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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公开(公告)号：US10803926B2
公开(公告)日：2020-10-13
申请号：US16237115
申请日：2018-12-31
发明人： Dale H. Hiscock , Debra M. Bell , Michael Kaminski , Joshua E. Alzheimer , Anthony D. Veches , James S. Rehmeyer
IPC分类号： G11C5/02 , G11C11/4093 , G11C11/406 , G11C7/18 , H01L25/10 , G11C11/4096
摘要： Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.
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公开(公告)号：US20200321049A1
公开(公告)日：2020-10-08
申请号：US16375716
申请日：2019-04-04
IPC分类号： G11C11/406 , G11C11/408
摘要： Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. A memory device may include a number of memory banks, at least some of which may be simultaneously entered into a refresh mode. A given memory bank may perform an auto-refresh operation or a targeted refresh operation, which may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered between the refreshing memory banks, such that a portion of the refreshing memory banks are performing a targeted refresh operation simultaneously with a portion of the refreshing memory banks performing an auto-refresh operation.
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76.发明申请公开(公告)号：US20200234738A1
公开(公告)日：2020-07-23
申请号：US16834293
申请日：2020-03-30
摘要： A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.
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公开(公告)号：US20200185024A1
公开(公告)日：2020-06-11
申请号：US16216894
申请日：2018-12-11
IPC分类号： G11C11/4094 , G11C11/406 , G11C11/4096 , G11C11/408
摘要： Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.
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78.发明授权公开(公告)号：US10541017B2
公开(公告)日：2020-01-21
申请号：US16543477
申请日：2019-08-16
IPC分类号： G11C7/00 , G11C11/406
摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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79.发明授权公开(公告)号：US10446248B1
公开(公告)日：2019-10-15
申请号：US15959921
申请日：2018-04-23
IPC分类号： G11C17/08 , G11C17/16 , G11C17/18 , G11C16/08 , G11C16/22 , G11C11/22 , G11C13/00 , G11C11/16
摘要： Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.
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80.发明授权公开(公告)号：US10297307B1
公开(公告)日：2019-05-21
申请号：US15870657
申请日：2018-01-12
IPC分类号： G11C7/00 , G11C11/406
摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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