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公开(公告)号：US20220020416A1
公开(公告)日：2022-01-20
申请号：US17387301
申请日：2021-07-28
发明人： Hyun Yoo Lee , Suryanarayana B. Tatapudi , Huy T. Vo , Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
IPC分类号： G11C11/22 , G11C11/4094 , G11C11/4091
摘要： Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
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公开(公告)号：US10984844B2
公开(公告)日：2021-04-20
申请号：US16452436
申请日：2019-06-25
发明人： Hyun Yoo Lee , Kang-Yong Kim
IPC分类号： G11C7/22 , G11C7/10 , G11C11/4076
摘要： Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
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73.发明授权公开(公告)号：US10860469B2
公开(公告)日：2020-12-08
申请号：US16448297
申请日：2019-06-21
IPC分类号： G06F12/00 , G11C11/4076 , G11C11/4096 , G11C11/4093 , G11C7/00 , G11C7/10 , G11C19/00 , G11C7/22 , G06F1/06 , G11C11/408 , G06F1/12
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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公开(公告)号：US20200075076A1
公开(公告)日：2020-03-05
申请号：US16121224
申请日：2018-09-04
发明人： Hyun Yoo Lee , Suryanarayana B. Tatapudi , Huy T. Vo , Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
IPC分类号： G11C11/22 , G11C11/4091 , G11C11/4094
摘要： Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
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75.发明授权公开(公告)号：US10534394B2
公开(公告)日：2020-01-14
申请号：US16138517
申请日：2018-09-21
IPC分类号： G06F1/06 , G11C11/4076 , G11C11/4096 , G11C11/4093 , G11C7/00 , G11C7/10 , G11C19/00 , G11C7/22 , G11C11/408 , G06F1/12
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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公开(公告)号：US20190385654A1
公开(公告)日：2019-12-19
申请号：US16551981
申请日：2019-08-27
发明人： Hyun Yoo Lee , Kang-Yong Kim
摘要： Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.
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77.发明申请公开(公告)号：US20190317545A1
公开(公告)日：2019-10-17
申请号：US16448297
申请日：2019-06-21
IPC分类号： G06F1/06 , G06F1/12 , G11C11/4096 , G11C11/4076 , G11C7/10 , G11C19/00 , G11C11/408 , G11C11/4093 , G11C7/22 , G11C7/00
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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78.发明申请公开(公告)号：US20190311753A1
公开(公告)日：2019-10-10
申请号：US16452436
申请日：2019-06-25
发明人： Hyun Yoo Lee , Kang-Yong Kim
IPC分类号： G11C7/22 , G11C11/4076 , G11C7/10
摘要： Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
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公开(公告)号：US10437514B2
公开(公告)日：2019-10-08
申请号：US15722769
申请日：2017-10-02
发明人： Kang-Yong Kim , Hyun Yoo Lee , John D. Porter
IPC分类号： G06F3/06 , G11C11/408 , G11C11/4076 , G11C11/4074
摘要： Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.
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公开(公告)号：US20190265913A1
公开(公告)日：2019-08-29
申请号：US16413475
申请日：2019-05-15
发明人： Kang-Yong Kim , Hyun Yoo Lee , John D. Porter
IPC分类号： G06F3/06
摘要： Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing, an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.
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