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1.发明申请公开(公告)号：US20190027197A1
公开(公告)日：2019-01-24
申请号：US16138517
申请日：2018-09-21
IPC分类号： G11C7/00 , G11C11/4093 , G11C11/4096 , G11C11/4076 , G06F1/12 , G11C19/00 , G11C7/10 , G11C11/408 , G11C7/22
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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公开(公告)号：US09740269B1
公开(公告)日：2017-08-22
申请号：US15498261
申请日：2017-04-26
CPC分类号： G06F1/3225 , G06F1/3296 , G06F11/348 , G06F13/1605 , G11C7/1057 , G11C7/1066 , G11C8/06 , G11C8/10 , G11C2207/2245 , G11C2207/2254
摘要： An arbitration system and method is disclosed. The apparatus includes first and second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.
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公开(公告)号：US20170109249A1
公开(公告)日：2017-04-20
申请号：US14883377
申请日：2015-10-14
CPC分类号： G06F1/3225 , G06F1/3296 , G06F11/348 , G06F13/1605 , G11C7/1057 , G11C7/1066 , G11C8/06 , G11C8/10 , G11C2207/2245 , G11C2207/2254
摘要： An arbitration system and method is disclosed. The apparatus includes first and second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.
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4.发明申请公开(公告)号：US20180247690A1
公开(公告)日：2018-08-30
申请号：US15445795
申请日：2017-02-28
IPC分类号： G11C11/4076 , G11C11/408 , G11C11/4096 , G06F1/12 , G11C11/4093
CPC分类号： G11C7/00 , G06F1/12 , G11C7/10 , G11C11/4076 , G11C11/4087 , G11C11/4093 , G11C11/4096 , G11C19/00
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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公开(公告)号：US20170228010A1
公开(公告)日：2017-08-10
申请号：US15498261
申请日：2017-04-26
CPC分类号： G06F1/3225 , G06F1/3296 , G06F11/348 , G06F13/1605 , G11C7/1057 , G11C7/1066 , G11C8/06 , G11C8/10 , G11C2207/2245 , G11C2207/2254
摘要： An arbitration system and method is disclosed. The apparatus includes first and second memory devices and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.
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公开(公告)号：US09665462B2
公开(公告)日：2017-05-30
申请号：US14883377
申请日：2015-10-14
CPC分类号： G06F1/3225 , G06F1/3296 , G06F11/348 , G06F13/1605 , G11C7/1057 , G11C7/1066 , G11C8/06 , G11C8/10 , G11C2207/2245 , G11C2207/2254
摘要： An arbitration system and method is disclosed. The apparatus includes first and second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.
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公开(公告)号：US10860469B2
公开(公告)日：2020-12-08
申请号：US16448297
申请日：2019-06-21
IPC分类号： G06F12/00 , G11C11/4076 , G11C11/4096 , G11C11/4093 , G11C7/00 , G11C7/10 , G11C19/00 , G11C7/22 , G06F1/06 , G11C11/408 , G06F1/12
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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公开(公告)号：US10534394B2
公开(公告)日：2020-01-14
申请号：US16138517
申请日：2018-09-21
IPC分类号： G06F1/06 , G11C11/4076 , G11C11/4096 , G11C11/4093 , G11C7/00 , G11C7/10 , G11C19/00 , G11C7/22 , G11C11/408 , G06F1/12
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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9.发明申请公开(公告)号：US20190317545A1
公开(公告)日：2019-10-17
申请号：US16448297
申请日：2019-06-21
IPC分类号： G06F1/06 , G06F1/12 , G11C11/4096 , G11C11/4076 , G11C7/10 , G11C19/00 , G11C11/408 , G11C11/4093 , G11C7/22 , G11C7/00
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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10.发明授权公开(公告)号：US10090026B2
公开(公告)日：2018-10-02
申请号：US15445795
申请日：2017-02-28
IPC分类号： G11C7/00 , G11C11/4076 , G11C11/408 , G11C11/4096 , G06F1/12 , G11C11/4093 , G11C7/10 , G11C19/00
摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
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