Abstract:
III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.
Abstract:
A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation and containing an oxygen surfactant layer to form a more uniform MgO layer and lower breakdown distribution percent. A CoFeB/NCC/CoFeB composite free layer with a middle nanocurrent channel layer minimizes Jc0 while enabling thermal stability, write voltage, read voltage, and Hc values that satisfy 64 Mb design requirements. The NCC layer has RM grains in an insulator matrix where R is Co, Fe, or Ni, and M is a metal such as Si or Al. NCC thickness is maintained around the minimum RM grain size to avoid RM granules not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A second NCC layer and third CoFeB layer may be included in the free layer or a second NCC layer may be inserted below the Ru capping layer.
Abstract:
A semi-conductor crystal and method of forming the same. The method includes providing a flow of dopant and column III element containing gases, then stopping flow of dopant and column III element containing gases, reducing the temperature, restarting flow of column III containing gases and then elevating the temperature.
Abstract:
A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.
Abstract:
A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.
Abstract:
A wireless data communications system includes simplified access points which are connected to ports of an intelligent switching hub. The switching hub relays data packets to the access points in accordance with destination address data in the data communications. In a preferred arrangement the access points are provided with power over the data cable from the switching hub location.
Abstract:
A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.
Abstract:
A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions.
Abstract:
A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.