公开(公告)号：US20190311908A1

公开(公告)日：2019-10-10

申请号：US16366539

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Maximillian CLEMONS ,  Mei-Yee SHEK ,  Minrui YU ,  Bencherki MEBARKI ,  Mehul B. NAIK ,  Chentsau YING ,  Srinivas D. NEMANI

IPC: H01L21/285 ,  H01L29/45

Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

公开(公告)号：US20190279879A1

公开(公告)日：2019-09-12

申请号：US16262094

申请日：2019-01-30

Applicant: Applied Materials, Inc.

Inventor： Kaushal K. SINGH ,  Mei-Yee SHEK ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/383 ,  H01L21/44 ,  C23C14/48 ,  C23C14/58

Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

公开(公告)号：US20190258153A1

公开(公告)日：2019-08-22

申请号：US16262102

申请日：2019-01-30

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Mei-Yee SHEK

IPC: G03F1/22 ,  G03F1/26

Abstract: The present disclosure provides methods for forming a material layer in a film stack for manufacturing a photomask in EUV applications and phase shift and binary photomask applications. In one example, a method for forming a dielectric material on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a dielectric material disposed on an optically transparent silicon containing material, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure at greater than 2 bar, and thermally treating the dielectric material in the presence of the oxygen containing gas mixture.

公开(公告)号：US20170092494A1

公开(公告)日：2017-03-30

申请号：US15377629

申请日：2016-12-13

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Uday MITRA ,  Praburam GOPALRAJA ,  Srinivas D. NEMANI ,  Hua CHUNG

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

公开(公告)号：US20170088949A1

公开(公告)日：2017-03-30

申请号：US14957440

申请日：2015-12-02

Applicant: Applied Materials, Inc.

Inventor： Viachslav BABAYAN ,  Qiwei LIANG ,  Tobin KAUFMAN-OSBORN ,  Ludovic GODET ,  Srinivas D. NEMANI

IPC: C23C16/448 ,  C23C16/44 ,  C23C16/458 ,  H01L21/687 ,  C23C16/46

CPC classification number: C23C16/4485 ,  C23C16/4401 ,  C23C16/4411 ,  C23C16/45517 ,  C23C16/4586 ,  C23C16/46 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67742 ,  H01L21/67754 ,  H01L21/68707 ,  H01L21/68764 ,  H01L21/68771

Abstract: The present disclosure generally relate to a semiconductor processing apparatus. In one embodiment, a processing chamber is disclosed herein. The processing chamber includes a chamber body and lid defining an interior volume, the lid configured to support a housing having a cap, a substrate support disposed in the interior volume, a vaporizer coupled to the cap and having an outlet open to the interior volume of the processing chamber, wherein the vaporizer is configured to deliver a precursor gas to a processing region defined between the vaporizer and the substrate support, and a heater disposed adjacent to the vaporizer, wherein the heater is configured to heat the vaporizer.

公开(公告)号：US20160293437A1

公开(公告)日：2016-10-06

申请号：US14968500

申请日：2015-12-14

Applicant: Applied Materials, Inc.

Inventor： Qingjun ZHOU ,  Jungmin KO ,  Tom CHOI ,  Sean KANG ,  Jeremiah PENDER ,  Srinivas D. NEMANI ,  Ying ZHANG

IPC: H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract translation: 本文描述的实施例涉及用于图案化衬底的方法。 诸如双重图案化和四重图案化工艺的图案化工艺可以受益于本文所述的实施例，其包括对间隔材料执行惰性等离子体处理，对间隔材料的处理区域进行蚀刻工艺，并重复惰性等离子体处理 和蚀刻工艺以形成期望的间隔物轮廓。 惰性等离子体处理工艺可以是偏压工艺，并且蚀刻工艺可以是无偏的工艺。 可以控制各种加工参数，例如工艺气体比和压力，以影响所需的间隔物轮廓。

公开(公告)号：US20160141202A1

公开(公告)日：2016-05-19

申请号：US14597149

申请日：2015-01-14

Applicant: Applied Materials, Inc.

Inventor： Jun XUE ,  Ludovic GODET ,  Erica CHEN ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/768 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/223

CPC classification number: H01L21/7682 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/32412 ,  H01J37/32422 ,  H01L21/2236 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/768 ,  H01L21/76825 ,  H01L23/5222

Abstract: Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate.

Abstract translation: 提供了使用离子注入工艺形成在互连结构的不同位置上形成的所需材料的互连结构中的空气间隙以限定蚀刻边界，然后进行半导体器件的蚀刻工艺的方法。 在一个实施例中，一种用于在衬底上形成互连结构中的气隙的方法，所述方法包括将离子注入设置在衬底上的绝缘材料的第一区域中，留下没有注入离子的第二区域，第二区域具有第一 与第一区域接合的表面和与衬底接合的第二表面，以及执行蚀刻工艺以选择性地蚀刻第二区域远离衬底，在第一区域和衬底之间形成气隙。

公开(公告)号：US20160139503A1

公开(公告)日：2016-05-19

申请号：US14589987

申请日：2015-01-05

Applicant: Applied Materials, Inc.

Inventor： Kartik RAMASWAMY ,  Srinivas D. NEMANI

IPC: G03F1/80

CPC classification number: G03F7/20 ,  G03F7/26 ,  H01J11/22 ,  H01J11/32 ,  H01J37/32541 ,  H01J37/32568 ,  H05H2001/2462 ,  H05H2001/485

Abstract: A method and apparatus disclosed herein apply to processing a substrate, and more specifically to a method and apparatus for improving photolithography processes. The apparatus includes a chamber body, a substrate support disposed within the chamber body, and an electrode assembly. The substrate support has a top plate disposed above the substrate support, a bottom plate disposed below the substrate support, and a plurality of electrodes connecting the top plate to the bottom plate. A voltage is applied to the plurality of electrodes to generate an electric field. Methods for exposing a photoresist layer on a substrate to an electric field are also disclosed herein.

Abstract translation: 本文公开的方法和装置适用于处理衬底，更具体地涉及用于改进光刻工艺的方法和装置。 该装置包括室主体，设置在室主体内的基板支撑件和电极组件。 衬底支撑件具有设置在衬底支撑件上方的顶板，设置在衬底支撑件下方的底板以及将顶板连接到底板的多个电极。 电压施加到多个电极以产生电场。 本文还公开了将基板上的光致抗蚀剂层暴露于电场的方法。

公开(公告)号：US20160005662A1

公开(公告)日：2016-01-07

申请号：US14736020

申请日：2015-06-10

Applicant: Applied Materials, Inc.

Inventor： Ellie Y. YIEH ,  Huixiong DAI ,  Srinivas D. NEMANI ,  Ludovic GODET ,  Christopher Dennis BENCHER

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/20

Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.

Abstract translation: 本公开的实施例提供了使用电子或离子注入的用于覆盖和边缘放置误差（EPE）的局部应力调制的装置和方法。 在一个实施例中，用于校正衬底上的覆盖误差的处理通常包括在衬底上的度量工具中执行测量过程以获得衬底失真或覆盖误差图，基于所述衬底失真或覆盖误差图确定掺杂参数以校正重叠误差或衬底失真 覆盖误差图，并且基于确定用于校正衬底失真或重叠误差的掺杂参数向掺杂装置提供掺杂配方。 实施例还可以使用确定的掺杂修复配方在衬底上执行掺杂处理过程，例如通过将覆盖误差图或衬底失真与存储在计算系统中的数据库进行比较。

公开(公告)号：US20150140827A1

公开(公告)日：2015-05-21

申请号：US14541978

申请日：2014-11-14

Applicant: Applied Materials, Inc.

Inventor： Chia-Ling KAO ,  Sean KANG ,  Jeremiah T. PENDER ,  Srinivas D. NEMANI ,  He REN ,  Mehul NAIK

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/32834 ,  H01J37/32871 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract translation: 本文描述的实施方式通常涉及半导体制造，更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中，提供了用于蚀刻阻挡层低k层的方法。 该方法包括（a）将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分，和（b）化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物，其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体，或至少包含氢气和三氟化氮气体。