公开(公告)号：US20150214101A1

公开(公告)日：2015-07-30

申请号：US14540577

申请日：2014-11-13

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Chia-Ling KAO ,  Sean KANG ,  Jeremiah T P PENDER ,  Srinivas D. NEMANI ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/308 ,  H01J37/32357 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract translation: 提供了用于消除双镶嵌结构中的导电层的早期暴露并用于蚀刻双镶嵌结构中的介电阻挡层的方法。 在一个实施例中，用于蚀刻设置在衬底上的电介质阻挡层的方法包括使用设置在介电体绝缘层上的硬掩模层作为蚀刻掩模来图案化设置在电介质阻挡层上的介电体绝缘层的衬底， 在去除绝缘体绝缘层未覆盖的绝缘体绝缘层之后，从基板去除硬掩模层，随后蚀刻由绝缘体绝缘层暴露的电介质阻挡层的部分介电阻挡层。

公开(公告)号：US20150140827A1

公开(公告)日：2015-05-21

申请号：US14541978

申请日：2014-11-14

Applicant: Applied Materials, Inc.

Inventor： Chia-Ling KAO ,  Sean KANG ,  Jeremiah T. PENDER ,  Srinivas D. NEMANI ,  He REN ,  Mehul NAIK

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/32834 ,  H01J37/32871 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract translation: 本文描述的实施方式通常涉及半导体制造，更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中，提供了用于蚀刻阻挡层低k层的方法。 该方法包括（a）将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分，和（b）化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物，其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体，或至少包含氢气和三氟化氮气体。

公开(公告)号：US20150064921A1

公开(公告)日：2015-03-05

申请号：US14015557

申请日：2013-08-30

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Sean S. KANG ,  Jeremiah T. P. PENDER ,  Chia-Ling KAO ,  Sergey G. BELOSTOTSKIY ,  Lina ZHU

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/3081 ,  H01L21/68742

Abstract: Methods for etching a material layer disposed on the substrate using a low temperature etching process along with a subsequent low temperature plasma annealing process are provided. In one embodiment, a method for etching a material layer disposed on a substrate includes transferring a substrate having a material layer disposed thereon into an etching processing chamber, supplying an etching gas mixture into the processing chamber, remotely generating a plasma in the etching gas mixture to etch the material layer disposed on the substrate, and plasma annealing the material layer at a substrate temperature less than 100 degrees Celsius.

Abstract translation: 提供了使用低温蚀刻工艺以及随后的低温等离子体退火工艺来蚀刻设置在基板上的材料层的方法。 在一个实施例中，用于蚀刻设置在基板上的材料层的方法包括将其上设置有材料层的基板转印到蚀刻处理室中，将蚀刻气体混合物供应到处理室中，在蚀刻气体混合物中远程产生等离子体 蚀刻设置在基板上的材料层，以及在低于100摄氏度的衬底温度下对材料层进行等离子体退火。