公开(公告)号：US20230131849A1

公开(公告)日：2023-04-27

申请号：US18145261

申请日：2022-12-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram ,  Paul Enquist

IPC: H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/683 ,  H01L25/065

Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

公开(公告)号：US20230118156A1

公开(公告)日：2023-04-20

申请号：US18069485

申请日：2022-12-21

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Gaius Gillman Fountain, JR. ,  Laura Wills Mirkarimi ,  Rajesh Katkar ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

公开(公告)号：US11552041B2

公开(公告)日：2023-01-10

申请号：US17096846

申请日：2020-11-12

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Gaius Gillman Fountain, Jr. ,  Chandrasekhar Mandalapu ,  Cyprian Emeka Uzoh ,  Jeremy Alfred Theil

IPC: H01L23/00

Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

公开(公告)号：US11515279B2

公开(公告)日：2022-11-29

申请号：US16995988

申请日：2020-08-18

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Liang Wang ,  Rajesh Katkar ,  Guilian Gao ,  Laura Wills Mirkarimi

IPC: H01L23/00

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

公开(公告)号：US12205926B2

公开(公告)日：2025-01-21

申请号：US18451674

申请日：2023-08-17

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Bongsub Lee ,  Gaius Gillman Fountain, Jr. ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Laura Wills Mirkarimi ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/482 ,  H01L23/522 ,  H01L21/60 ,  H01L25/00

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.

公开(公告)号：US20240429094A1

公开(公告)日：2024-12-26

申请号：US18822980

申请日：2024-09-03

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L21/768 ,  H01L21/68 ,  H01L23/00 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

Abstract: Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

公开(公告)号：US12125784B2

公开(公告)日：2024-10-22

申请号：US18451366

申请日：2023-08-17

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Gaius Gillman Fountain, Jr. ,  Jeremy Alfred Theil

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/298 ,  H01L23/3178 ,  H01L24/20

Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

公开(公告)号：US12113056B2

公开(公告)日：2024-10-08

申请号：US18145282

申请日：2022-12-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram ,  Paul Enquist

IPC: H01L25/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3081 ,  H01L21/561 ,  H01L21/683 ,  H01L23/3121 ,  H01L23/3135 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1304 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012

Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

公开(公告)号：US20240332248A1

公开(公告)日：2024-10-03

申请号：US18194571

申请日：2023-03-31

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/83 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/3135 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/80895 ,  H01L2224/83896 ,  H01L2924/182

Abstract: Direct bond interconnect in topographic packages and methods of making. The topographic packages include a first die hybrid bonded to a substrate, the first die located in a first device level. A second die located in a second device level above the first device, the second die hybrid bonded to the first die. The topographic packages also include a third die located in a third device level above the second die, the third die hybrid bonded to a top surface of the second device level.

公开(公告)号：US12080672B2

公开(公告)日：2024-09-03

申请号：US16874527

申请日：2020-05-14

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba ,  Laura Wills Mirkarimi ,  Javier A. DeLaCruz ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Thomas Workman

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/32 ,  H01L23/3107 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83896

Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.