公开(公告)号：US5557221A

公开(公告)日：1996-09-17

申请号：US76434

申请日：1993-06-14

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC: H03K19/0185 ,  H03F3/45

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract translation: 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及根据该开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US5537354A

公开(公告)日：1996-07-16

申请号：US357307

申请日：1994-12-14

Applicant: Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

Inventor： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Hiroyoshi Tomita

IPC: G11C11/401 ,  F02B75/02 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C13/00

CPC classification number: G11C7/1072 ,  F02B2075/025

Abstract: A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.

Abstract translation: 将SDRAM（同步动态随机存取存储器）制成低速型或高速型的方法包括以下步骤：确定SDRAM的预定电极的电连接，并为预定电极提供电压 由电气连接限定的电平，电压电平确定SDRAM是低速型还是高速型，其中低速类型可以以低时钟速率对具有 相同的行地址，并且高速类型可以以具有相同行地址和连续列地址的两个地址以高时钟速率执行同时写入操作。

公开(公告)号：US5307316A

公开(公告)日：1994-04-26

申请号：US861822

申请日：1992-06-16

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: H01L27/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/86 ,  G11C7/00

CPC classification number: G11C29/81 ,  G11C29/832

Abstract: A semiconductor memory device has a plurality of main memory blocks formed on a chip and each having a redundancy, a sub-memory block formed on the chip and having a substantially identical construction as that of each main memory block, a defect address memory circuit for storing address data of the main memory block that cannot be saved by the redundancy, and a redundancy control circuit for selecting the sub-memory block when a defective main memory block is selected.

Abstract translation: PCT No.PCT / JP91 / 01406 Sec。 371日期：1992年6月16日 102（e）日期1992年6月16日PCT 1991年10月16日PCT公布。 公开号WO92 / 07362 日期：1992年04月30日。半导体存储器件具有形成在芯片上并具有冗余的多个主存储器块，形成在芯片上的子存储块，并且具有与每个主存储器块相同的结构 ，用于存储不能由冗余保存的主存储块的地址数据的缺陷地址存储电路，以及当选择缺陷主存储块时用于选择子存储块的冗余控制电路。

公开(公告)号：US4982366A

公开(公告)日：1991-01-01

申请号：US467348

申请日：1990-01-22

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: G11C11/413 ,  G06F11/16 ,  G11C8/20 ,  G11C11/409 ,  G11C11/418 ,  G11C29/00 ,  G11C29/04 ,  H01L27/10

CPC classification number: G11C8/20 ,  G05B2219/25381

Abstract: A static semiconductor memory device includes a memory cell array including a large number of static memory cells arranged in a matrix fashion, a word decoder, a column decoder, and a data buffer. An address delay buffer is provided for delaying an input address signal by a predetermined delay time and a comparator circuit is provided for comparing the input address signal with the delayed address signal from the address delay buffer, so that even if the input address signal is disturbed by noise, the erroneous data corresponding to the disturbed address signal is not read into the data buffer by means of the output signal of the comparator circuit and is not output from the memory device.

Abstract translation: 静态半导体存储器件包括存储单元阵列，其包括以矩阵方式布置的大量静态存储器单元，字解码器，列解码器和数据缓冲器。 提供地址延迟缓冲器用于将输入地址信号延迟预定的延迟时间，并且提供比较器电路用于将输入地址信号与来自地址延迟缓冲器的延迟地址信号进行比较，使得即使输入地址信号被干扰 通过噪声，与干扰的地址信号相对应的错误数据不通过比较器电路的输出信号被读入数据缓冲器，并且不从存储器件输出。

公开(公告)号：US4970693A

公开(公告)日：1990-11-13

申请号：US484474

申请日：1990-02-23

Applicant: Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

Inventor： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

IPC: G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/40 ,  G11C11/413

CPC classification number: G11C7/22 ,  G11C8/18

Abstract: A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

Abstract translation: 半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。 输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。 输出电路具有连接到参考电位线的外部输出端子。 输出电路用于产生到外部输出端子的输出。 禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

公开(公告)号：US4879685A

公开(公告)日：1989-11-07

申请号：US311367

申请日：1989-02-16

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: G11C7/00 ,  G11C8/04 ,  G11C11/401 ,  H01L27/10

CPC classification number: G11C7/00 ,  G11C8/04

Abstract: A semiconductor memory device includes, a plurality of word lines, a plurality of bit lines and a plurality of memory cells each connected between the word lines and the bit lines at each intersection of the word lines and bit lines. A plurality of sense amplifiers, each connected to each pair of bit lines, are for amplifying a difference in potential between each of the bit lines; a plurality of bit line reset circuits, each connected to each pair of the bit lines, the difference in potential being held during the read/write cycles. A transfer mode setting circuit is for optionally selecting a first word line and thereafter selecting a second word line, and for simultaneously reading out data in each memory cell connected to the first word line onto each bit line and thereafter simultaneously writing data on each bit line amplified by the sense amplifier into each corresponding memory cell connected to the second word line.

Abstract translation: 半导体存储器件包括多个字线，多个位线和多个存储单元，每个位线和字线连接在字线和位线之间的字线和位线的每个交叉处。 每个连接到每对位线的多个读出放大器用于放大每个位线之间的电位差; 多个位线复位电路，每个连接到每对位线，在读/写周期期间电位差被保持。 传输模式设置电路用于可选地选择第一字线，然后选择第二字线，并且用于同时将连接到第一字线的每个存储单元中的数据读出到每个位线上，然后同时在每个位线上写入数据 由读出放大器放大成连接到第二字线的每个对应的存储单元。

公开(公告)号：US4807193A

公开(公告)日：1989-02-21

申请号：US81559

申请日：1987-02-25

Applicant: Yoshihiro Takemae ,  Takeo Takematsu ,  Kimiaki Sato ,  Takashi Horii ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada

Inventor： Yoshihiro Takemae ,  Takeo Takematsu ,  Kimiaki Sato ,  Takashi Horii ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada

IPC: G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C8/18 ,  G11C7/22

Abstract: A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.

Abstract translation: 具有用于检测字线的电位的检测电路的单晶体管单电容型半导体存储器件，以确定用于驱动读出放大器的适当定时，从而提高存储器操作的速度。

公开(公告)号：US4788667A

公开(公告)日：1988-11-29

申请号：US895113

申请日：1986-08-11

Applicant: Masao Nakano ,  Yoshihiro Takemae

Inventor： Masao Nakano ,  Yoshihiro Takemae

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  H01L29/00 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C7/1033

Abstract: In the semiconductor memory device havig a nibble mode function, memory cell arrays are divided into two groups of first and second cell blocks. Data bus lines are provided separately to each of the first and second cell blocks. Sense amplifiers are provided separately to each of the data bus lines. A column decoder, for connecting between bit lines, is provided in the memory cell array and corresponding data bus lines based on address signals and gate signals in a selection state. A switching circuit is provided for switching between sense amplifiers belonging to the first cell block and sense amplifiers belonging to the second cell block and for connecting these sense amplifiers to output buffers. A clock signal generating circuit is provided for generating the gate signals. The gate signals are generated in such a way that each gate signal is raised in response to a leading edge of a column address strobe signal and is allowed to fall in response to a trailing edge of the column address strobe signal in the nibble mode.

Abstract translation: 在具有半字节模式功能的半导体存储器件中，存储单元阵列被分成两组第一和第二单元块。 数据总线分别提供给第一和第二单元块中的每一个。 读出放大器分别提供给每条数据总线。 用于在位线之间连接的列解码器基于选择状态下的地址信号和门信号提供在存储单元阵列和对应的数据总线中。 提供了一种切换电路，用于切换属于第一单元块的读出放大器和属于第二单元块的读出放大器，并用于将这些读出放大器连接到输出缓冲器。 提供时钟信号发生电路以产生门信号。 门信号的生成方式是使每个门信号响应于列地址选通信号的前沿而升高，并且被允许响应于半字节模式中的列地址选通信号的后沿而下降。

公开(公告)号：US4787067A

公开(公告)日：1988-11-22

申请号：US883804

申请日：1986-07-09

Applicant: Yoshihiro Takemae ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

Inventor： Yoshihiro Takemae ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C11/406 ,  G11C11/4076

Abstract: A semiconductor dynamic memory device having an improved refreshing time is disclosed wherein the memory device provides two buffer memories exclusively for the external and refresh addresses, each of the buffer memories comprising a preamplifier and a driver stage. When the falling edge of a RAS signal is detected, all the circuits are enabled in parallel, but the operation of the driver is suppressed. As soon as a CAS before RAS detector discriminates which of the falling edges of the CAS and RAS signals becomes low earlier, it sends an address driving signal to one of the drivers, and the external address or refresh address are sent immediately. Using this technique, the prior art sequential operation of discriminating the falling edges of RAS and CAS signal, sending the refresh signal, receiving it and switching the circuit from external address to refresh address is eliminated, and is replaced by a parallel operation. Thus the set up time of the dynamic memory is reduced to 1-2 n.sec. by the present invention.

Abstract translation: 公开了一种具有改善的刷新时间的半导体动态存储器件，其中存储器件专门为外部和刷新地址提供两个缓冲存储器，每个缓冲存储器包括前置放大器和驱动器级。 当检测到＆upbar＆R信号的下降沿时，所有电路并联使能，但驱动器的操作被抑制。 只要一个＆upbar＆C＆amp;上＆gt;＆R检测器识别＆upbar＆C和＆lt; upbar＆R信号的哪个下降沿较早地变低，它向其中一个驱动器发送地址驱动信号，并立即发送外部地址或刷新地址 。 使用这种技术，消除了识别＆upbar＆R和＆amp; upbar＆C信号的下降沿，发送刷新信号，接收它并将电路从外部地址切换到刷新地址的现有技术的顺序操作，并且被并行操作替代。 因此，动态存储器的建立时间减少到1-2ns。 通过本发明。

公开(公告)号：US4760281A

公开(公告)日：1988-07-26

申请号：US11947

申请日：1987-02-06

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: H03K5/02 ,  H03K5/135 ,  H03K17/04 ,  H03K19/017 ,  H03K19/096 ,  H03K19/01

CPC classification number: H03K19/01735

Abstract: In a clock signal generating circuit for a semiconductor large scale integrated circuit, the clock signal generating circuit includes: a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a ground side power source line; a second N-channel transistor connected between a common connection point of the P-channel transistor and the first N-channel transistor and a gate of the first N-channel transistor through a node, and a clock signal is applied to a gate of the second N-channel transistor. A capacitor is connected between the gate of the first N-channel transistor and a gate of the P-channel transistor; and a bootstrap capacitor is connected to the common connection point.

Abstract translation: 在半导体大规模集成电路的时钟信号发生电路中，时钟信号发生电路包括：P沟道晶体管和第一N沟道晶体管，其串联连接在正侧电源线和接地侧电源 源线; 连接在P沟道晶体管的公共连接点和第一N沟道晶体管之间的第二N沟道晶体管和通过节点的第一N沟道晶体管的栅极，并且时钟信号被施加到 第二N沟道晶体管。 电容器连接在第一N沟道晶体管的栅极和P沟道晶体管的栅极之间; 并且自举电容器连接到公共连接点。