公开(公告)号：US07875520B2

公开(公告)日：2011-01-25

申请号：US12056277

申请日：2008-03-27

Applicant: Meng-Yi Wu ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Kun-Hsien Lee ,  Li-Shian Jeng ,  Shih-Jung Tu ,  Yu-Ming Lin ,  Yao-Chin Cheng

Inventor： Meng-Yi Wu ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Kun-Hsien Lee ,  Li-Shian Jeng ,  Shih-Jung Tu ,  Yu-Ming Lin ,  Yao-Chin Cheng

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L29/7848

Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.

Abstract translation: 公开了一种形成CMOS晶体管的方法。 提供具有第一有源区和第二有源区的CMOS晶体管。 为了保持第二有源区中的掺杂剂的浓度，根据本发明的方法，在形成外延层之后，在第二有源区中进行离子注入工艺以形成轻掺杂漏极（LDD） 第一个活跃区域。 另一方面，进行离子注入处理，以形成第一有源区和第二有源区的相应LDD。 在形成第一有源区中的外延层之后，再次执行另一种离子注入工艺以将掺杂剂注入到第二有源区的LDD中。

公开(公告)号：US07682890B2

公开(公告)日：2010-03-23

申请号：US11465455

申请日：2006-08-18

Applicant: Wen-Han Hung ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

Inventor： Wen-Han Hung ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

Abstract: A method of fabricating a semiconductor device is provided. A substrate is first provided, and then several IO devices and several core devices are formed on the substrate, wherein those IO devices include IO PMOS and IO NMOS, and those core devices include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.

Abstract translation: 提供一种制造半导体器件的方法。 首先提供衬底，然后在衬底上形成多个IO器件和多个核心器件，其中这些IO器件包括IO PMOS和IO NMOS，并且那些核心器件包括核心PMOS和核心NMOS。 此后，在衬底上形成缓冲层，然后除去IO PMOS的表面以外的缓冲层，以便减少IO PMOS的负偏压温度不稳定性（NBTI）。 之后，在IO NMOS和核心NMOS上形成一个拉伸接触蚀刻停止层（CESL），并且形成一个压电CESL的芯体PMOS。

公开(公告)号：US07642166B2

公开(公告)日：2010-01-05

申请号：US12265736

申请日：2008-11-06

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC: H01L213/8234

CPC classification number: H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

Abstract: A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

Abstract translation: 提供一种制造MOS晶体管器件的方法。 首先，准备具有栅极结构的半导体基板。 栅极结构在侧壁上具有两个侧壁和衬垫。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。 接下来，执行激活处理。 此外，将应力覆盖层蚀刻成为自对准硅化物块。 之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。

公开(公告)号：US07524716B2

公开(公告)日：2009-04-28

申请号：US11755669

申请日：2007-05-30

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

Abstract translation: 公开了一种半导体结构，包括其中具有第一导电类型的第一阱和第二导电类型的第二阱的衬底，第一导电类型的第一MOS晶体管和第二导电类型的第二MOS晶体管。 第一MOS晶体管设置在第二阱上，包括在第二阱上的栅极结构和位于栅极结构旁边的第二阱中的开口中的第一导电类型的应变层。 开口底部附近的应变层的一部分的单元参数与基板的单元参数之间的差值小于开口底部以外的应变层的一部分的单元参数之间的差， 底物。 第二MOS晶体管设置在第一阱上。

公开(公告)号：US07508053B2

公开(公告)日：2009-03-24

申请号：US11927642

申请日：2007-10-29

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC: H01L23/58

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract translation: 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 栅介质层形成在衬底的有源区上。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化物间隔物。 进行离子注入以形成源极/漏极区域。 在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。 去除氮化物间隔物。 与衬垫相邻的氮化物覆盖层被沉积。 氮化物盖层具有特定的应力状态。

公开(公告)号：US20090068805A1

公开(公告)日：2009-03-12

申请号：US12265736

申请日：2008-11-06

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

Abstract: A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

Abstract translation: 提供一种制造MOS晶体管器件的方法。 首先，准备具有栅极结构的半导体基板。 栅极结构在侧壁上具有两个侧壁和衬垫。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。 接下来，执行激活处理。 此外，将应力覆盖层蚀刻成为自对准硅化物块。 之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。

公开(公告)号：US20080242017A1

公开(公告)日：2008-10-02

申请号：US11690863

申请日：2007-03-26

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

IPC: H01L21/44 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of fabricating metal-oxide-semiconductor (MOS) transistor devices is disclosed. A semiconductor substrate is provided. A gate dielectric layer is formed. A gate electrode is stacked on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. Using the gate electrode and the silicon nitride spacer as an implantation mask, a source/drain is implanted into the substrate. After the source/drain implant, the silicon nitride spacer is then stripped. A silicide layer is formed on the source/drain region. Subsequently, a silicon nitride cap layer is deposited. The silicon nitride cap layer has a specific stress status.

Abstract translation: 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 提供半导体衬底。 形成栅介质层。 栅极电极层叠在栅极电介质层上。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 使用栅电极和氮化硅间隔物作为注入掩模，将源极/漏极注入到衬底中。 在源极/漏极注入之后，然后剥离氮化硅间隔物。 在源极/漏极区域上形成硅化物层。 随后，沉积氮化硅盖层。 氮化硅盖层具有特定的应力状态。

公开(公告)号：US20080197351A1

公开(公告)日：2008-08-21

申请号：US11675635

申请日：2007-02-16

Applicant: Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da- Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

Inventor： Shyh-Fann Ting ,  Sheng-Hao Lin ,  Chien-Hsing Lee ,  Da- Ching Chiou ,  Sun-Chin Wei ,  Min-Yi Chang ,  Cheng-Tung Huang ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng

IPC: H01L23/58

CPC classification number: H01L22/34

Abstract: A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

Abstract translation: 测试键设计模式包括至少一个导电触点，垂直并电连接到导电触点的至少一个第一宽度的导线和分别直接连接到导线的每一侧的至少一对源极和漏极。 一对源极和漏极以及直接连接到源极和漏极的第一长度的导电线的一部分形成电子器件。 测试键设计模式在测量电容时具有较小误差和更好的栅极氧化物厚度提取的优势。

公开(公告)号：US07410875B2

公开(公告)日：2008-08-12

申请号：US11400077

申请日：2006-04-06

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Tzyy-Ming Cheng

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.

Abstract translation: 对半导体结构体的制造方法进行说明。 提供了一种衬底，其上具有栅极结构和在栅极结构的侧壁上的隔离物，并且在栅极结构旁边具有S / D延伸区域。 在衬垫旁边的衬底上形成开口，然后在开口的底部形成有基底上的S / D区域。 在S / D区域和栅极结构上形成金属硅化物层，然后在基板上形成应力层。

公开(公告)号：US20080102588A1

公开(公告)日：2008-05-01

申请号：US11552957

申请日：2006-10-25

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Wen-Han Hung ,  Li-Shian Jeng ,  Tzyy-Ming Cheng

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Wen-Han Hung ,  Li-Shian Jeng ,  Tzyy-Ming Cheng

IPC: H01L21/336 ,  H01L21/425

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/6659

Abstract: A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.

Abstract translation: 一种用于形成MOS晶体管的方法，包括提供至少形成在其上的栅极结构的衬底，进行预非晶化（PAI）工艺以在衬底中形成非晶化区域，依次执行共注入工艺，第一离子注入工艺 以及第一快速热退火（RTA）工艺以形成轻掺杂的漏极（LDD），在栅极结构的侧壁上形成间隔物，并形成源极/漏极。