公开(公告)号：US20080185655A1

公开(公告)日：2008-08-07

申请号：US11670584

申请日：2007-02-02

Applicant: Shao-Ta Hsu ,  Teng-Chun Tsai ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Cheng-Han Wu ,  Wen-Han Hung

Inventor： Shao-Ta Hsu ,  Teng-Chun Tsai ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Cheng-Han Wu ,  Wen-Han Hung

IPC: H01L21/469 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/823807 ,  H01L29/7843

Abstract: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.

Abstract translation: 提供一种形成半导体器件的方法。 该方法包括以下步骤：提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底，然后在衬底上形成应力层以共形覆盖第一导电型晶体管和第二导电型晶体管 型晶体管。 在第一导电型晶体管上的应力层上形成覆盖层。 执行修改处理。 盖层被去除。

公开(公告)号：US07205634B2

公开(公告)日：2007-04-17

申请号：US10798959

申请日：2004-03-10

Applicant: Miao-Cheng Liao ,  Kuo-Hsien Cheng ,  Cheng-Chao Lin ,  Shao-Ta Hsu ,  Ying-Lang Wang

Inventor： Miao-Cheng Liao ,  Kuo-Hsien Cheng ,  Cheng-Chao Lin ,  Shao-Ta Hsu ,  Ying-Lang Wang

IPC: H01L29/00

CPC classification number: H01L28/40 ,  Y10S438/957

Abstract: An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to form a metal-insulator-metal (MIM) structure.

Abstract translation: 一种MIM结构及其形成方法，包括形成覆盖在半导体衬底上的底部导电电极; 在导电电极上形成第一保护层; 在所述第一保护层上形成电介质层; 并且在所述电介质层上形成上导电电极以形成金属绝缘体金属（MIM）结构。

公开(公告)号：US20050253268A1

公开(公告)日：2005-11-17

申请号：US10967009

申请日：2004-10-15

Applicant: Shao-Ta Hsu ,  Kuo-Hsien Cheng ,  Shwang-Ming Jeng ,  Hung-Tsai Liu ,  Wei-Cheng Chu ,  Yu-Ku Lin ,  Ying-Lang Wang

Inventor： Shao-Ta Hsu ,  Kuo-Hsien Cheng ,  Shwang-Ming Jeng ,  Hung-Tsai Liu ,  Wei-Cheng Chu ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure including a semiconductor substrate, a semiconductor active device formed in the substrate, a layer of low-k dielectric material, a first patterned conducting layer, a second patterned conducting layer, and a cap layer formed thereon. The low-k material layer is formed over the semiconductor device. The first conducting line is formed in the low-k material layer and connected to the semiconductor active device. The second conducting line is formed in the low-k material layer but not electrically connected to the semiconductor active device. The cap layer is formed over the low-k material layer, the first and second conducting lines. The cap layer includes silicon and carbon. Since the adhesion strength between the cap layer and the patterned conducting layer is greater than the adhesion strength between the cap layer and the low-k material layer, the addition of second patterned conducting layer would eliminate the overall possibility of delamination between the surface where cap layer is in contact with the low-k material and the first and the second patterned conducting layers.

Abstract translation: 包括半导体衬底，形成在衬底中的半导体有源器件，低k电介质材料层，第一图案化导电层，第二图案化导电层和形成在其上的帽层的半导体互连结构。 低k材料层形成在半导体器件上。 第一导线形成在低k材料层中并连接到半导体有源器件。 第二导线形成在低k材料层中，但不与半导体有源器件电连接。 盖层形成在低k材料层，第一和第二导电线之上。 盖层包括硅和碳。 由于盖层和图案化导电层之间的粘合强度大于覆盖层和低k材料层之​​间的粘合强度，所以添加第二图案化导电层将消除在盖的表面之间的分层的总体可能性 层与低k材料和第一和第二图案化导电层接触。

公开(公告)号：US07541298B2

公开(公告)日：2009-06-02

申请号：US11621968

申请日：2007-01-10

Applicant: Shao-Ta Hsu ,  Neng-Kuo Chen ,  Teng-Chun Tsai

Inventor： Shao-Ta Hsu ,  Neng-Kuo Chen ,  Teng-Chun Tsai

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/31612 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/76224

Abstract: A method for filling silicon oxide materials into a trench includes providing a substrate having a plurality of trenches, performing a first deposition process to form a first silicon oxide layer in the trenches, and performing a second deposition process to form a second silicon oxide layer in the trenches. The reactant gas of the first deposition process has a first O3/TEOS flow ratio larger than a second O3/TEOS flow ratio of the reactant gas of the second deposition process.

Abstract translation: 将氧化硅材料填充到沟槽中的方法包括提供具有多个沟槽的衬底，执行第一沉积工艺以在沟槽中形成第一氧化硅层，以及执行第二沉积工艺以形成第二氧化硅层 壕沟 第一沉积工艺的反应气体具有比第二沉积工艺的反应气体的第二O 3 / TEOS流量比大的第一O 3 / TEOS流动比。

公开(公告)号：US07494878B2

公开(公告)日：2009-02-24

申请号：US11552532

申请日：2006-10-25

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC: H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

Abstract: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

Abstract translation: 一种制造MOS晶体管器件的方法。 首先，准备具有栅极结构的半导体基板。 栅极结构在侧壁上具有两个侧壁和衬垫。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。 接下来，执行激活处理。 此外，将应力覆盖层蚀刻成为自对准硅化物块。 之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。

公开(公告)号：US20080188091A1

公开(公告)日：2008-08-07

申请号：US12043905

申请日：2008-03-06

Applicant: SHAO-TA HSU ,  Teng-Chun Tsai ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Cheng-Han Wu ,  Wen-Han Hung

Inventor： SHAO-TA HSU ,  Teng-Chun Tsai ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Cheng-Han Wu ,  Wen-Han Hung

IPC: H01L21/469

CPC classification number: H01L27/092 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/823807 ,  H01L29/7843

Abstract: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.

Abstract translation: 提供一种形成半导体器件的方法。 该方法包括以下步骤：提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底，然后在衬底上形成应力层以共形覆盖第一导电型晶体管和第二导电型晶体管 型晶体管。 在第一导电型晶体管上的应力层上形成覆盖层。 执行修改处理。 盖层被去除。

公开(公告)号：US20070020875A1

公开(公告)日：2007-01-25

申请号：US11161074

申请日：2005-07-21

Applicant: Shao-Ta Hsu ,  Neng-Kuo Chen ,  Teng-Chun Tsai

Inventor： Shao-Ta Hsu ,  Neng-Kuo Chen ,  Teng-Chun Tsai

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: A seamless trench fill method utilizing ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) technique is provided. After the deposition of a SACVD silicon oxide film, the substrate is subjected to a steam anneal that is performed under H2O2 environment at a relatively lower temperature ranging between 500° C. and 800° C. for a time period of no less than 30 minutes. The seam defect in the trench is effectively eliminated by this low-temperature steam anneal. To densify the SACVD silicon oxide film, a subsequent N2 anneal is carried out at a higher temperature, for example, 1050° C.

Abstract translation: 提供了利用臭氧辅助亚大气压化学气相沉积（SACVD）技术的无缝沟槽填充方法。 在沉积SACVD氧化硅膜之后，将衬底经受在H 2 O 2 O 2环境下进行的蒸汽退火，温度在500° C.和800℃，时间不少于30分钟。 通过这种低温蒸汽退火有效地消除了沟槽中的接缝缺陷。 为了致密化SACVD氧化硅膜，随后的N 2 H 3退火在更高的温度例如1050℃下进行。

公开(公告)号：US20130161786A1

公开(公告)日：2013-06-27

申请号：US13333564

申请日：2011-12-21

Applicant: Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I. Hsieh ,  Ching Kai Lin

Inventor： Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I. Hsieh ,  Ching Kai Lin

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L27/10817 ,  H01L27/105 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract translation: 电容器阵列包括多个电容器和支撑框架。 每个电容器包括电极。 支撑框架支撑多个电极，并且包括对应于多个电极的多个支撑结构。 每个支撑结构可以围绕相应的电极。 支撑框架可以包括掺杂可氧化材料的氧化物。

公开(公告)号：US20080166888A1

公开(公告)日：2008-07-10

申请号：US11621968

申请日：2007-01-10

Applicant: Shao-Ta Hsu ,  Neng-Kuo Chen ,  Teng-Chun Tsai

Inventor： Shao-Ta Hsu ,  Neng-Kuo Chen ,  Teng-Chun Tsai

IPC: H01L21/31

CPC classification number: H01L21/31612 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/76224

Abstract: A method for filling silicon nitride materials into a trench includes providing a substrate having a plurality of trenches, performing a first deposition process to form a first silicon nitride layer in the trenches, and performing a second deposition process to form a second silicon nitride layer in the trenches. The reactant gas of the first deposition process has a first O3/TEOS flow ratio larger than a second O3/TEOS flow ratio of the reactant gas of the second deposition process.

Abstract translation: 将氮化硅材料填充到沟槽中的方法包括提供具有多个沟槽的衬底，执行第一沉积工艺以在沟槽中形成第一氮化硅层，以及执行第二沉积工艺以形成第二氮化硅层 壕沟 第一沉积工艺的反应气体具有大于第二沉积工艺的反应气体的第二O 3 / TEOS流动比的第一O 3 / TEOS流动比 。

公开(公告)号：US20080099801A1

公开(公告)日：2008-05-01

申请号：US11552532

申请日：2006-10-25

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Neng-Kuo Chen ,  Shao-Ta Hsu ,  Teng-Chun Tsai ,  Chien-Chung Huang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

Abstract: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

Abstract translation: 一种制造MOS晶体管器件的方法。 首先，准备具有栅极结构的半导体衬底。 栅极结构在侧壁上具有两个侧壁和衬垫。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。 接下来，执行激活处理。 此外，将应力覆盖层蚀刻成为自对准硅化物块。 之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。