公开(公告)号：US20240170440A1

公开(公告)日：2024-05-23

申请号：US18373405

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanyoung CHOI ,  Seokhyun LEE ,  Seokgeun AHN

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/33 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/3303 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/2064

Abstract: A semiconductor package includes first semiconductor chips electrically connected to each other through a through-via electrically connecting a first front surface pad and a first rear surface pad. A second semiconductor chip has a second lower surface including a second front surface pad, a second upper surface, a second side surface extending from the second upper surface, and a recess surface extending from the second lower surface to the second side surface. First adhesive films are on a first lower surface of first semiconductor chips and include first extension portions extending further outwardly than a first side surface of the first semiconductor chips. A second adhesive film is on the second lower surface and includes a second extension portion extending further outwardly than the second side surface. In a horizontal direction, a length of the second extension portion is less than a length of each of the first extension portions.

公开(公告)号：US20240170360A1

公开(公告)日：2024-05-23

申请号：US18422166

申请日：2024-01-25

Applicant: MEDIATEK Inc.

Inventor： Chun-Yin LIN ,  Yu-Jin LI ,  Tai-Yu CHEN ,  Pu-Shan HUANG

IPC: H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2224/29012 ,  H01L2224/29035 ,  H01L2224/32225 ,  H01L2224/32257 ,  H01L2224/33055 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83104

Abstract: A semiconductor device includes a substrate, an electronic component, a cover and a liquid metal. The electronic component is disposed on the substrate. The cover is disposed on the substrate, coves the electronic component and has a recess. The liquid metal is formed between the recess and the electronic component.

公开(公告)号：US11990177B2

公开(公告)日：2024-05-21

申请号：US18195877

申请日：2023-05-10

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US20240162180A1

公开(公告)日：2024-05-16

申请号：US18413887

申请日：2024-01-16

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/24227 ,  H01L2224/73209 ,  H01L2224/92124

Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.

公开(公告)号：US20240153863A1

公开(公告)日：2024-05-09

申请号：US18219211

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungok JUNG ,  Jakyoung GU

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49866 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package including, a first redistribution substrate including a first body layer and a first wiring layer in the first body layer, a semiconductor chip on the first redistribution substrate, a through post around the semiconductor chip and on the first redistribution substrate, and a second redistribution substrate on the semiconductor chip and the through post, wherein, the first wiring layer includes a first titanium seed layer, and the first titanium seed layer has a vertical cross-section of a trapezoid structure in which a top surface is narrow and a bottom surface is wide.

公开(公告)号：US11978729B2

公开(公告)日：2024-05-07

申请号：US17370282

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Heh-Chang Huang ,  Fu-Jen Li ,  Pei-Haw Tsao ,  Shyue-Ter Leu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.

公开(公告)号：US11978699B2

公开(公告)日：2024-05-07

申请号：US17406150

申请日：2021-08-19

Applicant: Texas Instruments Incorporated

Inventor： Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Sreenivasan K. Koduri

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L21/6835 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2224/81385 ,  H01L2224/81815

Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

公开(公告)号：US20240145448A1

公开(公告)日：2024-05-02

申请号：US18407760

申请日：2024-01-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Heh-Chang HUANG ,  Fu-Jen LI ,  Pei-Haw TSAO ,  Shyue-Ter LEU

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.

公开(公告)号：US20240145358A1

公开(公告)日：2024-05-02

申请号：US17973641

申请日：2022-10-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203

Abstract: A package structure and a method of manufacturing a package structure are provided. The package structure includes a substrate and an electronic component. The substrate includes a patterned circuit layer and defines a through hole. An extending portion of the patterned circuit layer extends along a sidewall of the through hole. The electronic component has an active surface over the through hole of the substrate. The active surface of the electronic component is electrically connected to the patterned circuit layer of the substrate through the extending portion of the patterned circuit layer in the through hole.

公开(公告)号：US20240136326A1

公开(公告)日：2024-04-25

申请号：US18399189

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Wei LI ,  Edvin CETEGEN ,  Nicholas S. HAEHN ,  Ram S. VISWANATH ,  Nicholas NEAL ,  Mitul MODI

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.