公开(公告)号：US20180005670A1

公开(公告)日：2018-01-04

申请号：US15199802

申请日：2016-06-30

Applicant: Futurewei Technologies, Inc.

Inventor： Xiaobing Lee ,  Feng Yang ,  Yu Meng ,  Yunxiang Wu

IPC: G11C7/10 ,  G06F3/06 ,  G06F11/14 ,  G11C5/04 ,  G11C8/18 ,  G06F12/02 ,  G06F13/16

CPC classification number: G11C7/10 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0655 ,  G06F3/0685 ,  G06F11/1469 ,  G06F12/0246 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/005 ,  G11C2029/0411 ,  G11C2207/2245

Abstract: An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.

公开(公告)号：US20180004599A1

公开(公告)日：2018-01-04

申请号：US15621757

申请日：2017-06-13

Applicant: Nantero, Inc.

Inventor： Sheyang NING

IPC: G06F11/10 ,  G11C29/52 ,  G11C13/00

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/44 ,  G11C29/52 ,  G11C2013/0083 ,  G11C2029/0407 ,  G11C2029/0411 ,  G11C2213/71 ,  G11C2213/79 ,  G11C2213/82

Abstract: Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.

公开(公告)号：US20180004596A1

公开(公告)日：2018-01-04

申请号：US15197446

申请日：2016-06-29

Applicant: Micron Technology, Inc.

Inventor： Yihua Zhang ,  Paolo E. Mangalindan ,  Jianfei Lei ,  Andrew D. Proescholdt ,  Gerard A. Kreifels

IPC: G06F11/10 ,  G11C29/50 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/50 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.

公开(公告)号：US09858142B2

公开(公告)日：2018-01-02

申请号：US15062557

申请日：2016-03-07

Applicant: SK hynix Inc.

Inventor： Min Su Park

IPC: G06F11/10 ,  G11C11/406 ,  G11C11/408 ,  H03M13/00

CPC classification number: G06F11/1044 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4085 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/20 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/789 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2211/4062 ,  H03M13/6566

Abstract: Provided is a semiconductor device including an error correction code circuit. The semiconductor device includes a bank including a memory area for storing data and an error correction for storing parity data, an error correction code calculation circuit that corrects an error of a failed cell in correspondence to the data and the parity data and outputs a flag signal activated at a time of a generation of failed data and an address activated in the bank, an address latch circuit that stores the address applied from the error correction code calculation circuit and outputs a failed address according to the flag signal, and a fail prevention circuit that performs an operation for repairing the failed data in correspondence to the flag signal and the failed address.

公开(公告)号：US20170365329A1

公开(公告)日：2017-12-21

申请号：US15640250

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  John B. Halbert

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C11/4076 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.

公开(公告)号：US09842660B1

公开(公告)日：2017-12-12

申请号：US13841026

申请日：2013-03-15

Applicant: Virident Systems Inc.

Inventor： Vijay Karamcheti ,  Ashish Singhai ,  Ashwin Narasimha ,  Muthugopalkrishnan Adiseshan ,  Viswesh Sankaran ,  Ajith Kumar

IPC: G06F11/00 ,  G11C29/04 ,  G06F11/30 ,  G06F11/34 ,  G06F11/07

CPC classification number: G11C29/04 ,  G06F11/0757 ,  G06F11/3034 ,  G06F11/34 ,  G06F11/3409 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A method for managing a non-volatile random-access memory (NVRAM)-based storage subsystem, the method including: monitoring, by a slave controller on a NVRAM device of the NVRAM-based storage subsystem, an I/O operation on the NVRAM device; identifying, by the slave controller and based on the monitoring, at least one occurrence of error data; comparing, by the slave controller, a numeric aspect of the at least one occurrence of error data with a threshold setting; reporting, by the slave controller on the NVRAM device and to a master controller of the NVRAM-based storage subsystem, the at least one occurrence of error data in response to the numeric aspect crossing the threshold setting; and ascertaining, by the master controller of the NVRAM-based storage system, a physical location of a defect region on the NVRAM device where the error data has occurred by analyzing the reported at least one occurrence of error data.

公开(公告)号：US20170351570A1

公开(公告)日：2017-12-07

申请号：US15174462

申请日：2016-06-06

Applicant: Micron Technology, Inc.

Inventor： Ryan S. Laity ,  Christopher S. Johnson

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/38 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: Apparatuses and methods are described for selective determination of data error repair. An example apparatus includes a memory array and a controller coupled to the memory array. The controller is configured to direct performance, responsive to a request, of a read operation at an address in the memory array, direct detection of an error in data corresponding to the read operation address, and direct storage of the read operation address in an address error register. The controller is further configured to direct a response be sent to the enable selective determination of data error repair, where the response does not include the read operation address.

公开(公告)号：US09836351B2

公开(公告)日：2017-12-05

申请号：US15076415

申请日：2016-03-21

Applicant: NandEXT S.r.l.

Inventor： Margherita Maffeis

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F3/0679 ,  G06F11/1012 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1105 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/458 ,  H03M13/6325

Abstract: A method is proposed for decoding bits stored in memory cells of a solid state drive. Each memory cell comprises a floating gate transistor adapted to store a bit pattern, among a plurality of possible bit patterns, when programmed at a threshold voltage associated with that bit pattern, each threshold voltage being variable over the memory cells thereby defining, for each bit pattern, a corresponding threshold voltage distribution. The bit pattern of each memory cell comprises first and second bits, and the solid state drive is suitable for reading the bit patterns based on fixed reference voltages, each one designed to discern between two respective adjacent threshold voltage distributions, and on additional reference voltages different from the fixed reference voltages. The solid state drive is capable of soft decoding the read bit patterns based on soft information.

公开(公告)号：US09836349B2

公开(公告)日：2017-12-05

申请号：US14724899

申请日：2015-05-29

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Chi-Shun Lin

IPC: G06F11/10 ,  G11C11/00 ,  G11C13/00 ,  G11C29/04 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50 ,  G11C29/52 ,  G11C7/04

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C7/04 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0033 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0407 ,  G11C2029/0411

Abstract: A memory system includes a resistive nonvolatile memory array configured to store data and error correction code (ECC) bits and a memory controller. The memory controller is configured to detect a number of errors among the stored look-ahead bits, compare the number of look-ahead bit errors to a threshold number of bit errors, perform a strong refresh of the data and look-ahead bits stored in the resistive nonvolatile memory array when the number of look-ahead bit errors equals or exceeds the threshold, and perform a weak refresh of the data and look-ahead bits by refreshing only units of stored data having data bit errors and look-ahead bits having look-ahead bit errors when the number of look-ahead bit errors is less than the threshold.

公开(公告)号：US09812224B2

公开(公告)日：2017-11-07

申请号：US14800614

申请日：2015-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Jin Yun

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  G11C16/34 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/108 ,  G11C16/3418 ,  G11C2029/0411

Abstract: Provided are a data storage system, a data storage device and a RAID controller, which can control RAID operation and a RAID operating method of a memory device by transmitting a RAID configuration signal to the memory device. The data storage system includes a memory device that may include m nonvolatile memories, where m is a natural number, and a memory controller that may program data to at least the first to mth pages. The data storage system also includes a RAID controller that may generate a RAID configuration signal, including a RAID operation signal for determining whether to activate or deactivate a RAID operation of the memory device, and that may transmit the data and the RAID configuration signal to the memory controller. The memory controller may generate a RAID parity using first to (m−1)th data from the RAID controller and program the first to (m−1)th data to the first to (m−1)th pages and the RAID parity to the mth page when the RAID operation signal is activated, but program the first to mth data received from the RAID controller to the first to mth pages when the RAID operation signal is deactivated.