公开(公告)号：US20140112072A1

公开(公告)日：2014-04-24

申请号：US14058227

申请日：2013-10-19

Applicant: Aplus Flash Technology, Inc

Inventor： Hsing-Ya Tsao ,  Peter Wung Lee

IPC: G11C14/00

CPC classification number: G11C14/0063

Abstract: A 10T NVSRAM cell is provided with a bottom HV NMOS Select transistor in each 3T FString removed from traditional 12T NVSRAM cell. A Recall operation by reading a stored ΔVt state of flash transistors into each SRAM cell uses a charge-sensing scheme rather than the current-sensing scheme, with all other key operations unchanged. The Recall operation works under any ramping rate of SRAM's power line voltage and Flash gate signal which can be set higher than only Vt0 or both Vt0 and Vt1. Alternatively, the Store operation can use a current charging scheme from a Fpower line to the paired Q and QB nodes of each SRAM cell through a paired Flash Voltage Follower that stored ΔVtp≧1.0V. The Recall operation in this alternative embodiment is to use a 7-step approach with the FN-channel erase, FN-channel program and FN-edge program schemes, including 2-step SRAM amplification.

Abstract translation: 10T NVSRAM单元提供有从传统12T NVSRAM单元移除的每个3T FString中的底部HV NMOS选择晶体管。 通过将闪存晶体管的存储的＆Dgr; Vt状态读入每个SRAM单元的回收操作使用电荷感测方案而不是电流感测方案，其他所有关键操作都不变。 调用操作在SRAM的电源线电压和闪存栅极信号的任何斜坡率下工作，其可以被设置为高于仅Vt0或者Vt0和Vt1两者。 或者，存储操作可以使用存储＆Dgr;Vtp≥1.0V的成对闪存电压跟随器从Fpower线路到每个SRAM单元的成对Q和QB节点的当前充电方案。 该替代实施例中的调用操作是使用包括2步SRAM放大的FN通道擦除，FN通道程序和FN边缘程序方案的7步法。

公开(公告)号：US20140085978A1

公开(公告)日：2014-03-27

申请号：US14037356

申请日：2013-09-25

Applicant: Peter Wung Lee

Inventor： Peter Wung Lee

IPC: G11C14/00

CPC classification number: G11C14/0063 ,  G11C11/005 ,  G11C15/046 ,  G11C16/0483 ,  H01L21/0262 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/115

Abstract: Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two separate sourcelines for the paired flash Strings are also proposed for easy adding ability for the NVSRAM circuit to detect the marginally erased Vt0 and marginally programmed Vt1 of the paired flash cell. By increasing an resistance added to common SRAM power line, the pull-down current through flash Strings to grounding source line can be made much larger than the pull-up current to improve SFwrite program operation. Simple method by increasing flash cell channel length to effectively enhance coupling area is applied to secure SRAM-to-Flash store operation under self-boost-program-inhibit scheme. 1S2F architecture also provide flexibility for alternate erasing and programming during both a recall and store operation.

Abstract translation: 提出了1S1F 16T NVSRAM，1S1F 20T NVSRAM，1S2F 22T NVSRAM，1S2F 14T NVSRAM单元的几个优选实施例，而不管1-聚，2-聚，PMOS或NOS闪存单元结构如何。 还提出了用于配对闪存串的两个独立的源线，用于容易地添加NVSRAM电路检测成对闪存单元的边缘擦除Vt0和边缘编程Vt1的能力。 通过增加普通SRAM电源线的电阻，通过闪光串的下拉电流到接地源线可以比上拉电流大得多，以改善SFwrite程序运行。 通过增加闪存单元通道长度以有效增强耦合面积的简单方法被应用于在自增强编程抑制方案下保护SRAM到闪存存储器操作。 1S2F架构还为召回和存储操作期间的交替擦除和编程提供了灵活性。

公开(公告)号：US08331150B2

公开(公告)日：2012-12-11

申请号：US12319241

申请日：2009-01-05

Applicant: Fu-Chang Hsu ,  Peter Wung Lee

Inventor： Fu-Chang Hsu ,  Peter Wung Lee

IPC: G11C14/00

CPC classification number: G11C14/00 ,  G11C14/0063 ,  Y10T29/49002

Abstract: A nonvolatile SRAM circuit has an SRAM cell and one or two FLOTOX EEPROM cells connected to the data storage terminals of the SRAM cell. In programming to a first data level, the threshold voltage of a FLOTOX EEPROM transistor is brought to a programmed voltage level greater than a read voltage level and erasing to a second data level, the threshold voltage of the FLOTOX EEPROM transistor is brought to an erased voltage level less than the read voltage level. The nonvolatile SRAM array provides for restoring data to an SRAM cell from a FLOTOX EEPROM memory cell(s) at a power initiation and storing data to the FLOTOX EEPROM memory cell(s) to the SRAM cell at power termination. A power detection circuit for providing signals indicating power initiation and power termination to instigate restoration and storing of data between an SRAM cell and a FLOTOX EEPROM cell(s).

Abstract translation: 非易失性SRAM电路具有连接到SRAM单元的数据存储端的SRAM单元和一个或两个FLOTOX EEPROM单元。 在编程到第一数据电平时，FLOTOX EEPROM晶体管的阈值电压达到大于读取电压电平并被擦除到第二数据电平的编程电压电平，FLOTOX EEPROM晶体管的阈值电压被擦除 电压电平小于读取电压电平。 非易失性SRAM阵列用于在功率发生时从FLOTOX EEPROM存储单元向SRAM单元恢复数据，并在断电时将数据存储到SRAM单元中的FLOTOX EEPROM存储单元。 一种功率检测电路，用于提供指示功率启动和功率终止的信号，以在SRAM单元和FLOTOX EEPROM单元之间启动数据的恢复和存储。

公开(公告)号：US08315096B2

公开(公告)日：2012-11-20

申请号：US13216546

申请日：2011-08-24

Applicant: James D Allan ,  Jayant Ashokkumar

Inventor： James D Allan ,  Jayant Ashokkumar

IPC: G11C14/00

CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

Abstract: The state of a volatile memory cell is set by grounding a power supply to the volatile memory cell and driving a first bit line to the volatile memory cell to a first defined state. The first defined state of the first bit line is controllable independently of a defined state of a second bit line to the volatile memory cell. A word line of the volatile memory cell is driven to a word line state, and the power supply to the volatile memory cell is ungrounded.

Abstract translation: 通过将电源接地到易失性存储器单元并将第一位线驱动到易失性存储器单元至第一限定状态来设置易失性存储器单元的状态。 第一位线的第一定义状态可以独立于到易失性存储器单元的第二位线的定义状态来控制。 易失性存储器单元的字线被驱动到字线状态，并且向易失性存储单元的电源不接地。

公开(公告)号：US20120020159A1

公开(公告)日：2012-01-26

申请号：US13011726

申请日：2011-01-21

Applicant: Adrian E. Ong

Inventor： Adrian E. Ong

IPC: G11C14/00 ,  H01R43/00

CPC classification number: G11C14/0081 ,  G11C14/0063 ,  G11C14/0072 ,  G11C14/009 ,  Y10T29/49117

Abstract: A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.

Abstract translation: 一种非易失性静态随机存取存储器单元，包括耦合到第一和第二晶体管以及第一和第二非易失性存储单元的双稳态再生电路。 使用方法包括在非易失性存储单元和双稳态再生电路之间直接传送互补数据位。 或者，来自双稳态再生电路的补充数据可以在被传送到存储器单元列中的非易失性存储器单元之前由读出放大器和第二双稳态再生电路再生。 双稳态再生电路可能被复位到地电位。 使用从双稳态再生电路直接读出的非易失性SRAM单元的应用包括非易失性触发器或非易失性复用器。

公开(公告)号：US20110148463A1

公开(公告)日：2011-06-23

申请号：US12966513

申请日：2010-12-13

Applicant: Kiyoshi Kato ,  Jun Koyama

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H03K19/173

CPC classification number: H03K19/1733 ,  G11C14/0063 ,  G11C16/02 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/7869 ,  H03K3/356008 ,  H03K3/35606

Abstract: A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.

Abstract translation: 提供了一种新颖的非易失性锁存电路和使用非易失性锁存电路的半导体器件。 锁存电路具有环形结构，其中第一元件的输出电连接到第二元件的输入，并且第二元件的输出通过第二晶体管电连接到第一元件的输入端。 使用使用氧化物半导体作为沟道形成区域的半导体材料的晶体管作为开关元件，并且提供电容器以电连接到晶体管的源电极或漏电极，由此锁存电路的数据可以 并且可以形成非易失性锁存电路。

公开(公告)号：US07518916B2

公开(公告)日：2009-04-14

申请号：US11644819

申请日：2006-12-22

Applicant: Jayant Ashokkumar ,  David W. Still ,  James D. Allan ,  John Roger Gill

Inventor： Jayant Ashokkumar ,  David W. Still ,  James D. Allan ,  John Roger Gill

IPC: G11C16/04

CPC classification number: G11C14/00 ,  G11C14/0063

Abstract: A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Abstract translation: 公开了一种用于对半导体存储器中的非易失性部分的两侧进行编程的系统和方法。 本发明擦除然后对nvSRAM的非易失性部分中的存储器堆栈进行编程。

公开(公告)号：US07512000B2

公开(公告)日：2009-03-31

申请号：US11735910

申请日：2007-04-16

Applicant: Ming-Chang Kuo

Inventor： Ming-Chang Kuo

IPC: G11C16/04

CPC classification number: H01L27/1112 ,  G11C14/00 ,  G11C14/0063 ,  H01L27/1104 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/792

Abstract: A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The memory unit not only has the advantage of high speed operation of a static random access memory, but also functions as a non-volatile memory for saving data.

Abstract translation: 本文提供了存储单元。 本发明利用具有分离栅极结构的两个非易失性器件来保存存储器单元的逻辑状态。 因此，即使当存储器单元的电源被关闭时，非易失性设备仍然可以保存逻辑状态。 存储单元不仅具有静态随机存取存储器的高速操作的优点，而且还用作用于保存数据的非易失性存储器。

公开(公告)号：US07408815B2

公开(公告)日：2008-08-05

申请号：US11740458

申请日：2007-04-26

Applicant: William C. Plants

Inventor： William C. Plants

IPC: G11C7/10

CPC classification number: G11C14/00 ,  G11C11/412 ,  G11C14/0063 ,  H03K19/1776

Abstract: First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.

Abstract translation: 第一和第二互补静态随机存取存储器单元位线通过由字线控制的第一和第二存取晶体管耦合到第一和第二位节点。 第一反相器具有耦合到第一位节点的输入和耦合到第二位节点的输出。 第二反相器具有耦合到第二位节点的输入和通过第一晶体管开关耦合到第一位节点的输出。 晶体管开关耦合在非易失性存储单元的输出和第一位节点之间。 耦合到晶体管开关的栅极的控制电路。 选择非易失性存储单元的驱动电平以使第二反相器的输出过压，或者第二反相器与第一位节点去耦，而非易失性存储单元的输出耦合到第一位节点。

公开(公告)号：US07408801B2

公开(公告)日：2008-08-05

申请号：US11834542

申请日：2007-08-06

Applicant: Hee Bok Kang ,  Jin Hong Ahn

Inventor： Hee Bok Kang ,  Jin Hong Ahn

IPC: G11C11/00 ,  G11C11/34

CPC classification number: G11C11/413 ,  G11C7/20 ,  G11C14/00 ,  G11C14/0063 ,  H01L29/7881

Abstract: A nonvolatile semiconductor memory device is provided for a high-powered system without the need for an additional system setting process to set the system initialization state after power-on to the previous state. The nonvolatile semiconductor memory device comprises a pull-up driving unit configured to include a plurality of nonvolatile cells for storing inputted data and to pull up a storage node, a pull-down driving unit configured to pull down the storage node, and a plurality of data registers including a data input/output unit configured to selectively input/output data between a bit line and the storage node depending on a voltage applied to a word line.

Abstract translation: 为大功率系统提供非易失性半导体存储器件，而不需要额外的系统设置过程，以在上电之后将系统初始化状态设置为先前状态。 非易失性半导体存储器件包括：上拉驱动单元，被配置为包括用于存储输入数据和上拉存储节点的多个非易失性单元，被配置为将存储节点拉下来的下拉驱动单元，以及多个 数据寄存器，包括数据输入/输出单元，其配置为根据施加到字线的电压来选择性地在位线和存储节点之间输入/输出数据。