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    ON-DIE COMPUTER APPARATUS
    61.
    发明公开
    ON-DIE COMPUTER APPARATUS 审中-公开

    公开(公告)号：US20230168915A1

    公开(公告)日：2023-06-01

    申请号：US17923979

    申请日：2021-05-18

    Applicant: BAE SYSTEMS PLC

    Inventor： Simon BISHOP

    IPC: G06F9/455 ,  G06F12/10 ,  G06F12/14

    CPC classification number: G06F9/45558 ,  G06F12/10 ,  G06F12/1408 ,  G06F2009/45587 ,  G06F2212/1052

    Abstract: An on-die computer apparatus (100) comprises a plurality of cores (106) and a plurality of RAM modules (100). Sets of physical memory addresses in the RAM modules are allocated for use by virtual machines executing on the cores. A plurality of data transfer channels (112) are associated the RAM modules. The apparatus further comprises a channel controller (120) for controlling data transfer over the data transfer channels. The channel controller stores security information indicating which of the VMs is designated as secure, and channel information indicating which of the data transfer channels is assigned for use by each of the VMs for accessing its allocated physical memory addresses. The channel controller directs read/write requests from a VM over the data transfer channel assigned to the VM based on the security information and the channel information.

    Memory system and operation method thereof
    64.
    发明授权
    Memory system and operation method thereof 有权

    公开(公告)号：US11650929B2

    公开(公告)日：2023-05-16

    申请号：US17245307

    申请日：2021-04-30

    Applicant: SK hynix Inc.

    Inventor： Ju Hyun Kim

    IPC: G06F12/10 ,  G06F3/06

    CPC classification number: G06F12/10 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/657

    Abstract: A memory system includes: a memory device including a plurality of memory dies including the plurality of planes; and a controller configured to store data in a plurality of stripes each including physical pages of different planes and a plurality of unit regions, the controller comprising: a processor configured to queue write commands in a write queue, and select, among the plurality of stripes, a stripe in which data chunks corresponding to the write commands are to be stored; and a striping engine configured to receive queued orders of the write commands, and output, by referring to a lookup table, addresses of unit regions, in which the data chunks are to be arranged, to the processor, wherein the processor in configured to control the memory device to store the data chunks in the unit regions corresponding to the outputted addresses of the selected stripe.

    Data Integrity Protection Of SSDs Utilizing Streams
    65.
    发明公开
    Data Integrity Protection Of SSDs Utilizing Streams 审中-公开

    公开(公告)号：US20230147206A1

    公开(公告)日：2023-05-11

    申请号：US18093734

    申请日：2023-01-05

    Applicant: Western Digital Technologies, Inc.

    Inventor： Daniel L. HELMICK ,  Peter GRAYSON

    IPC: G06F3/06 ,  G06F12/0804 ,  G06F12/10 ,  G06F1/30

    CPC classification number: G06F3/065 ,  G06F12/0804 ,  G06F3/0604 ,  G06F12/10 ,  G06F1/30 ,  G06F3/068 ,  G06F2212/657 ,  G06F2212/1032

    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. When a write command is received to write data to a stream, change log data is generated and stored in the RAM1, the previous delta data for the stream is copied from the RAM2 to the RAM1 to be updated with the change log data, and the updated delta data is copied to the RAM2. The delta data stored in the RAM2 is copied to the storage unit periodically. The controller tracks which delta data has been copied to the RAM2 and to the storage unit. During a power failure, the delta data and the change log data are copied from the RAM1 or the RAM2 to the storage unit.

    UNIVERSAL POINTERS FOR DATA EXCHANGE IN A COMPUTER SYSTEM HAVING INDEPENDENT PROCESSORS
    66.
    发明公开
    UNIVERSAL POINTERS FOR DATA EXCHANGE IN A COMPUTER SYSTEM HAVING INDEPENDENT PROCESSORS 审中-公开

    公开(公告)号：US20230146488A1

    公开(公告)日：2023-05-11

    申请号：US18148701

    申请日：2022-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Steven Jeffrey Wallach

    IPC: G06F9/38 ,  G06F9/34 ,  G06F12/10 ,  G06F9/30

    CPC classification number: G06F9/3836 ,  G06F9/34 ,  G06F12/10 ,  G06F9/30043 ,  G06F2212/657 ,  G06F2212/1008

    Abstract: A system, method and apparatus to facilitate data exchange via pointers. For example, in a computing system having a first processor and a second processor that is separate and independent from the first processor, the first processor can run a program configured to use a pointer identifying a virtual memory address having an ID of an object and an offset within the object. The first processor can use the virtual memory address to store data at a memory location in the computing system and/or identify a routine at the memory location for execution by the second processor. After the pointer is communicated from the first processor to the second processor, the second processor can access the same memory location identified by the virtual memory address. The second processor may operate on the data stored at the memory location or load the routine from the memory location for execution.

    SCALE-OUT TYPE STORAGE SYSTEM
    67.
    发明申请
    SCALE-OUT TYPE STORAGE SYSTEM 审中-公开

    公开(公告)号：US20190235793A1

    公开(公告)日：2019-08-01

    申请号：US16330791

    申请日：2017-02-23

    Applicant: HITACHI, LTD.

    Inventor： Ryo AIKAWA ,  Yo SHIGETA

    IPC: G06F3/06 ,  G06F12/10

    CPC classification number: G06F3/0661 ,  G06F3/06 ,  G06F3/0608 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/08 ,  G06F12/10 ,  G06F2212/657

    Abstract: A first node transmitting a non-extension read command which is a read command for reading out data without extending, and in which command a logical address is designated that corresponds to compressed data, to a first nonvolatile memory device. The first node transmits a transfer command to a second node via a network. The transfer command is for transferring between nodes the data to be transferred, the transferred object being the compressed data read out without extending by the first nonvolatile memory device in response to the non-extended read command. The second node transmits, in response to the transfer command, a write command for which the compressed data is the target to write to a second nonvolatile memory device.

    Technology For Managing Memory Tags
    68.
    发明申请
    Technology For Managing Memory Tags 审中-公开

    公开(公告)号：US20190196977A1

    公开(公告)日：2019-06-27

    申请号：US16288844

    申请日：2019-02-28

    Applicant: Intel Corporation

    Inventor： Kai Cong ,  Karanvir Grewal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  David Michael Durham

    IPC: G06F12/10 ,  G06F11/10 ,  G06F3/06 ,  G06F21/60

    CPC classification number: G06F12/10 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/0673 ,  G06F11/1076 ,  G06F21/602 ,  G06F2212/657

    Abstract: A data processing system includes support for sub-page granular memory tags. The data processing system comprises at least one core, a memory controller responsive to the core, random access memory (RAM) responsive to the memory controller, and a memory protection module in the memory controller. The memory protection module enables the memory controller to use a memory tag value supplied as part of a memory address to protect data stored at a location that is based on a location value supplied as another part of the memory address. The data processing system also comprises an operating system (OS) which, when executed in the data processing system, manages swapping a page of data out of the RAM to non-volatile storage (NVS) by using a memory tag map (MTM) to apply memory tags to respective subpages within the page being swapped out. Other embodiments are described and claimed.

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