公开(公告)号：US20140167210A1

公开(公告)日：2014-06-19

申请号：US13897360

申请日：2013-05-18

申请人： Semiconductor Manufacturing International Corp.

发明人： DANIEL HU

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： Various embodiments provide a semiconductor structure and fabrication method. An exemplary semiconductor structure can include a semiconductor substrate having an isolation trench formed in the semiconductor substrate. A first barrier layer can be disposed on a bottom surface and a sidewall of the isolation trench. A light absorption layer can be disposed at least on a surface portion of the first barrier layer over the bottom surface of the isolation trench. A second barrier layer can fill the isolation trench to form an isolation structure in the semiconductor substrate. The isolation structure can have a top surface flushed with or over a top surface of the semiconductor substrate.

摘要翻译： 各种实施例提供半导体结构和制造方法。 示例性的半导体结构可以包括在半导体衬底中形成有隔离沟槽的半导体衬底。 第一阻挡层可以设置在隔离沟槽的底表面和侧壁上。 光吸收层可以至少设置在隔离沟槽的底表面上的第一阻挡层的表面部分上。 第二阻挡层可以填充隔离沟槽，以在半导体衬底中形成隔离结构。 隔离结构可以具有在半导体衬底的顶表面上或之上冲洗的顶表面。

公开(公告)号：US20140151637A1

公开(公告)日：2014-06-05

申请号：US13831995

申请日：2013-03-15

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.

发明人： DEYUAN XIAO

IPC分类号： H01L29/66 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/7783

摘要： A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.

摘要翻译： 提供了一种用于制造晶体管的方法。 该方法包括提供半导体衬底，并在半导体衬底上形成量子阱层。 该方法还包括在半导体衬底上形成势能阻挡层，并形成隔离结构以隔离不同的晶体管区域。 此外，该方法包括通过去除与源极区和漏极区相对应的量子阱层和势能势垒层的部分来形成沟槽，以形成沟槽，并且用半导体材料填充沟槽以形成源极和漏极 。 此外，该方法还包括在量子阱层的一部分上形成栅极结构和对应于栅极区的势垒层。

公开(公告)号：US20140144474A1

公开(公告)日：2014-05-29

申请号：US14166981

申请日：2014-01-29

申请人： Semiconductor Manufacturing International Corp.

发明人： ZHUGEN YUAN

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/02063

摘要： Various embodiments provide methods and systems for making and/or cleaning semiconductor devices. In one embodiment, a semiconductor device can be formed including a metal layer and a photoresist polymer. During formation, the semiconductor device can be cleaned in a cleaning chamber by a first cleaning solution provided from a solution supply device. After this cleaning process, a second cleaning solution containing metal ions and/or polymer residues can be produced and processed in a solution processing device to at least partially remove the metal ions and/or polymer residues to produce a third cleaning solution for re-use. In an exemplary fabrication or cleaning system, the solution processing device may be configured connecting to either an inlet or an outlet of the cleaning chamber. After cleaning, the semiconductor device can be processed to include a metal plug or an interconnect wiring.

摘要翻译： 各种实施例提供用于制造和/或清洁半导体器件的方法和系统。 在一个实施例中，可以形成包括金属层和光致抗蚀剂聚合物的半导体器件。 在形成期间，可以通过从溶液供应装置提供的第一清洁溶液在清洁室中清洁半导体器件。 在该清洁过程之后，可以在溶液处理装置中产生并处理含有金属离子和/或聚合物残余物的第二清洁溶液，以至少部分地除去金属离子和/或聚合物残余物，以产生用于再次使用的第三清洁溶液 。 在示例性制造或清洁系统中，溶液处理装置可以被配置为连接到清洁室的入口或出口。 在清洁之后，半导体器件可被处理成包括金属插头或互连线。

公开(公告)号：US08560992B2

公开(公告)日：2013-10-15

申请号：US13685731

申请日：2012-11-27

申请人： Jingheng Wei ,  Zheqiu Liu

发明人： Jingheng Wei ,  Zheqiu Liu

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081

摘要： A method is provided for inspecting a chip layout. The method includes providing a chip layout having a plurality of patterns designed according to a design rule and performing a first inspection to the plurality of patterns according to the design rule. The method also includes determining patterns violating the design rule, as violating patterns, and corresponding violation values, and determining violating patterns having a minimum violation value among the violating patterns. Further, the method includes classifying the violating patterns having the minimum violation value into at least one sub-category based on characteristics of the violating patterns having the minimum violation value, and performing a second inspection on a selected violating pattern from the sub-category to determine whether the selected violating pattern and other violating patterns in the sub-category satisfy fabrication process conditions.

摘要翻译： 提供了一种用于检查芯片布局的方法。 该方法包括提供具有根据设计规则设计的多个图案的芯片布局，并根据设计规则对多个图案执行第一次检查。 该方法还包括确定违反设计规则的模式，违反模式和相应的违规值，以及确定违规模式中具有最小违规值的违规模式。 此外，该方法包括基于具有最小违规值的违规模式的特征将具有最小违规值的违规模式分类为至少一个子类别，并且对从所选子类别到所选择的违规模式进行第二检查 确定子类别中所选择的违规模式和其他违规模式是否满足制造工艺条件。

公开(公告)号：US09640425B2

公开(公告)日：2017-05-02

申请号：US14166981

申请日：2014-01-29

申请人： Semiconductor Manufacturing International Corp

发明人： Zhugen Yuan

IPC分类号： B08B3/00 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76814 ,  H01L21/02063

摘要： Various embodiments provide methods and systems for making and/or cleaning semiconductor devices. In one embodiment, a semiconductor device can be formed including a metal layer and a photoresist polymer. During formation, the semiconductor device can be cleaned in a cleaning chamber by a first cleaning solution provided from a solution supply device. After this cleaning process, a second cleaning solution containing metal ions and/or polymer residues can be produced and processed in a solution processing device to at least partially remove the metal ions and/or polymer residues to produce a third cleaning solution for re-use. In an exemplary fabrication or cleaning system, the solution processing device may be configured connecting to either an inlet or an outlet of the cleaning chamber. After cleaning, the semiconductor device can be processed to include a metal plug or an interconnect wiring.

公开(公告)号：US09348240B2

公开(公告)日：2016-05-24

申请号：US13686096

申请日：2012-11-27

申请人： Yibin Huang ,  Winnie Liu

发明人： Yibin Huang ,  Winnie Liu

IPC分类号： G03F9/00

CPC分类号： G03F9/7049 ,  G03F9/7003

摘要： An alignment method includes dividing a wafer into a plurality of regions including a first region and a second region, and each region contains a plurality chip areas. The method also includes obtaining alignment offset values for the first region, and determining a first alignment compensation equation for the first region. The method also includes obtaining alignment offset values for the second region, and determining a second alignment compensation equation for the second region. Further, the method includes determining whether a chip area to be exposed is in the first region or the second region, when the chip area is in the first region, using the first alignment compensation equation to adjust alignment of the wafer and, when the chip area is in the second region, using the second alignment compensation equation to adjust the alignment of the wafer.

摘要翻译： 对准方法包括将晶片分成包括第一区域和第二区域的多个区域，并且每个区域包含多个芯片区域。 该方法还包括获得第一区域的对准偏移值，以及确定第一区域的第一对准补偿方程。 该方法还包括获得第二区域的对准偏移值，以及确定第二区域的第二对准补偿方程。 此外，该方法包括：使用第一对准补偿方程来调整晶片的对准，当芯片面积在第一区域中时，确定要暴露的芯片面积是否在第一区域或第二区域中，并且当芯片 区域在第二区域中，使用第二对准补偿方程来调整晶片的对准。

公开(公告)号：US09312328B2

公开(公告)日：2016-04-12

申请号：US13831987

申请日：2013-03-15

申请人： Semiconductor Manufacturing International Corp.

发明人： Qiyang He

IPC分类号： H01L21/461 ,  H01L29/02 ,  H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0337 ,  H01L29/02

摘要： A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.

摘要翻译： 提供了一种用于制造小间距图案的方法。 该方法包括提供半导体衬底，并在半导体衬底上形成具有第一区域和第二区域的靶材料层。 该方法还包括在目标材料层的第一区域上形成多个离散的第一牺牲层和在目标材料层的第二区域上形成多个离散的第二牺牲层，以及在离散的两侧上形成第一侧壁间隔物 第一牺牲层和离散的第二牺牲层。 此外，该方法包括去除第一牺牲层和第二牺牲层，以及形成第二侧壁间隔物。 此外，该方法还包括在目标材料层的第一区域中形成离散的重复图案，并且在目标材料层的第二区域中形成连续图案。

公开(公告)号：US09147737B2

公开(公告)日：2015-09-29

申请号：US13914868

申请日：2013-06-11

申请人： Semiconductor Manufacturing International Corp.

发明人： Aries Chen

IPC分类号： H01L29/40 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/02

CPC分类号： H01L29/401 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/823462 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor substrate can then be placed in an atomic layer deposition (ALD) chamber to repeatedly perform a selective ALD process. The selective ALD process can include an etching process and/or a purging process in the ALD chamber. By repeatedly performing the selective ALD process, a first high-K dielectric layer can be selectively formed on the first silicon oxide layer in the first region, exposing the semiconductor substrate in the second region.

摘要翻译： 各种实施例提供包括高K电介质层和制造方法的半导体器件。 可以通过提供包括第一区域和第二区域的半导体衬底以及在第一区域中的半导体衬底上形成第一氧化硅层来形成示例性的高K电介质层。 然后可以将半导体衬底放置在原子层沉积（ALD）室中以重复执行选择性ALD工艺。 选择性ALD工艺可以包括在ALD室中的蚀刻工艺和/或清洗工艺。 通过重复执行选择性ALD工艺，可以在第一区域中的第一氧化硅层上选择性地形成第一高K电介质层，使第二区域中的半导体衬底露出。

公开(公告)号：US09134624B2

公开(公告)日：2015-09-15

申请号：US13730818

申请日：2012-12-28

申请人： Semiconductor Manufacturing International Corp.

发明人： Qiang Wu ,  Jing'an Hao ,  Chang Liu ,  Xin Yao ,  Tianhui Li ,  Qiang Shu ,  Yiming Gu

IPC分类号： G03B27/42 ,  G03B27/68 ,  G03B27/54 ,  G03B27/32 ,  G03F7/20 ,  G03B27/58 ,  G03B27/62

CPC分类号： G03F7/70358

摘要： The present disclosure provides a lithography machine and a scanning and exposing method thereof. According to the scanning and exposing method, the scanning and exposing process for a whole wafer includes two alternately circulated motions: a scanning and exposing motion and a stepping motion; and the scanning and exposing motion is a sinusoidal motion rather than a rapid-acceleration uniform-speed rapid-deceleration scanning and exposing motion in the conventional techniques. During the scanning of a single exposure shot, it may begin to scan the exposure shot once a wafer stage and a reticle stage begin to accelerate from zero speed. And the scanning and exposing may not end until the speeds of the wafer stage and the reticle decrease to zero. Therefore, the effective time of the scanning and exposing in the scanning and exposing motion is greatly increased and the production efficiency of the wafer is improved.

摘要翻译： 本公开提供了一种光刻机及其扫描和曝光方法。 根据扫描和曝光方法，整个晶片的扫描和曝光处理包括两个交替循环的运动：扫描和曝光运动以及步进运动; 并且扫描和曝光运动是常规技术中的正弦运动而不是快速加速均匀速度的快速减速扫描和曝光运动。 在单次曝光拍摄的扫描期间，一旦晶片台和标线片阶段从零速度开始加速，它可能开始扫描曝光。 并且扫描和曝光可能不会结束，直到晶片台和掩模版的速度降至零。 因此，扫描和曝光运动中的扫描和曝光的有效时间大大增加，并且提高了晶片的生产效率。

公开(公告)号：US09129994B2

公开(公告)日：2015-09-08

申请号：US13777142

申请日：2013-02-26

申请人： Semiconductor Manufacturing International Corp.

发明人： Wenbo Wang

IPC分类号： H01L21/20 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785

摘要： A fin field effect transistor (FET) including a fin structure and a method for forming the fin FET are provided. In an exemplary method, the fin FET can be formed by forming at least one fin seed, including a top surface and sidewalls, on a substrate. A first semiconductor layer can then be formed at least on the sidewalls of the at least one fin seed. A second semiconductor layer can be formed on the first semiconductor layer. The second semiconductor layer and the at least one fin seed can be made of a same material. The first semiconductor layer can be removed to form a fin structure including the at least one fin seed and the second semiconductor layer.

摘要翻译： 提供了包括翅片结构的翅片场效应晶体管（FET）和用于形成鳍式FET的方法。 在一种示例性方法中，翅片FET可以通过在衬底上形成包括顶表面和侧壁的至少一个翅片种子来形成。 然后可以至少在至少一个翅片种子的侧壁上形成第一半导体层。 可以在第一半导体层上形成第二半导体层。 第二半导体层和至少一个翅片种子可以由相同的材料制成。 可以去除第一半导体层以形成包括至少一个翅片种子和第二半导体层的翅片结构。