公开(公告)号：US20080142896A1

公开(公告)日：2008-06-19

申请号：US11612643

申请日：2006-12-19

Applicant: Xiangdong Chen ,  Young G. Ko ,  Haining Yang

Inventor： Xiangdong Chen ,  Young G. Ko ,  Haining Yang

IPC: H01L27/11

CPC classification number: H01L27/11 ,  H01L29/7847 ,  Y10S257/903

Abstract: An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.

Abstract translation: 提供了包括SRAM单元的集成电路（IC）结构，其中栅极晶体管的性能降低，以便增加SRAM单元内的晶体管的β比。 特别地，本发明中通过有意地仅改善下拉晶体管的性能，同时降低栅极晶体管的性能来获得增加的β比。 通过在逻辑互补金属氧化物半导体（CMOS）nFET和SRAM下拉晶体管上实施应力记忆技术来提高nFET性能，在本发明中实现了该结果。 在pFET区域不进行应力记忆技术，以避免性能下降以及在SRAM栅极晶体管中避免改进。 随着下拉晶体管的性能改善，传递栅极晶体管的性能得不到改善，SRAM晶体管的β比率得到了改善。

公开(公告)号：US07388267B1

公开(公告)日：2008-06-17

申请号：US11612643

申请日：2006-12-19

Applicant: Xiangdong Chen ,  Young G. Ko ,  Haining Yang

Inventor： Xiangdong Chen ,  Young G. Ko ,  Haining Yang

IPC: H01L29/78

CPC classification number: H01L27/11 ,  H01L29/7847 ,  Y10S257/903

Abstract: An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.

Abstract translation: 提供了包括SRAM单元的集成电路（IC）结构，其中栅极晶体管的性能降低，以便增加SRAM单元内的晶体管的β比。 特别地，本发明中通过有意地仅改善下拉晶体管的性能，同时降低栅极晶体管的性能来获得增加的β比。 通过在逻辑互补金属氧化物半导体（CMOS）nFET和SRAM下拉晶体管上实施应力记忆技术来提高nFET性能，在本发明中实现了该结果。 在pFET区域不进行应力记忆技术，以避免性能下降以及在SRAM栅极晶体管中避免改进。 随着下拉晶体管的性能改善，传递栅极晶体管的性能得不到改善，SRAM晶体管的β比率得到了改善。

公开(公告)号：US20080083991A1

公开(公告)日：2008-04-10

申请号：US11538550

申请日：2006-10-04

Applicant: Haining Yang ,  Jack A. Mandelman ,  Wai-Kin Li

Inventor： Haining Yang ,  Jack A. Mandelman ,  Wai-Kin Li

IPC: H01L23/52

CPC classification number: H01L21/76895 ,  B82Y10/00 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/11 ,  H01L27/1104

Abstract: The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.

Abstract translation: 本发明涉及一种具有第一和第二有源器件区域的半导体器件，该半导体器件区域位于半导体衬底中并且通过它们之间的隔离区彼此隔离，而半导体器件包含宽度范围的第一子光刻互连结构 从约20nm至约40nm，用于将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一子光刻互连结构直接将SRAM单元的下拉晶体管与其上拉晶体管交叉连接 其间没有任何金属接触。 可以通过掩模层的光刻图案容易地形成第一亚光刻互连结构，然后使用自组装嵌段共聚物或电介质侧壁间隔物形成亚光刻特征。

公开(公告)号：US20080036017A1

公开(公告)日：2008-02-14

申请号：US11836193

申请日：2007-08-09

Applicant: Hung Ng ,  Haining Yang

Inventor： Hung Ng ,  Haining Yang

IPC: H01L31/00

CPC classification number: H01L29/665 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/0629 ,  H01L29/6656

Abstract: A semiconductor device. The semiconductor device includes a substrate includes: a substrate having a first gate stack on a surface of the substrate, wherein the first gate stack has a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack; a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate; an insulative layer on a second portion of the surface of the substrate; and a conductive layer on the top surface of the first gate stack.

Abstract translation: 半导体器件。 该半导体器件包括：衬底，其包括：在衬底的表面上具有第一栅极堆叠的衬底，其中第一栅极堆叠具有平行于衬底的表面的顶表面和垂直于衬底表面的侧壁; 在第一栅极堆叠的侧壁上并且不在第一栅极堆叠的顶表面上的耐蚀刻的第一衬垫; 在所述第一衬垫上方的第一外隔离物，其中所述第一衬垫设置在所述第一外隔离物和所述第一栅叠层的侧壁之间，并且其中所述第一衬垫的一部分覆盖所述衬底的所述表面的第一部分; 在所述基板的表面的第二部分上的绝缘层; 以及在第一栅极堆叠的顶表面上的导电层。

公开(公告)号：US20080034335A1

公开(公告)日：2008-02-07

申请号：US11875013

申请日：2007-10-19

Applicant: Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

Inventor： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

IPC: G11C29/54

CPC classification number: H01L29/78603 ,  G11C29/54 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772

Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.

Abstract translation: 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。 设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。

公开(公告)号：US07309901B2

公开(公告)日：2007-12-18

申请号：US10908087

申请日：2005-04-27

Applicant: Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

Inventor： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC: H01L21/8232

CPC classification number: H01L29/7833 ,  H01L29/665 ,  H01L29/6659

Abstract: A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。 形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触 区域和第二S / D扩展区域。 对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。 类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

公开(公告)号：US20070252212A1

公开(公告)日：2007-11-01

申请号：US11380278

申请日：2006-04-26

Applicant: David Onsongo ,  Werner Rausch ,  Haining Yang

Inventor： David Onsongo ,  Werner Rausch ,  Haining Yang

IPC: H01L23/62

CPC classification number: H01L29/7391 ,  H01L29/66356

Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

Abstract translation: 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度 导体。

公开(公告)号：US20070246752A1

公开(公告)日：2007-10-25

申请号：US11379655

申请日：2006-04-21

Applicant: Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

Inventor： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

IPC: H01L29/76

CPC classification number: H01L29/66545 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603 ,  Y10S438/96

Abstract: Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.

Abstract translation: 具有减小的结电容和漏极引起的屏障降低的半导体器件结构，用于制造这种器件结构的方法以及用于形成绝缘体上半导体衬底的方法。 半导体结构包括半导体层和设置在半导体层和衬底之间的电介质层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。 在一个实施例中，第一电介质区域的介电常数可以小于约3.9，并且第二电介质区域的介电常数可以大于约十（10）。 绝缘体上半导体衬底包括通过高介电常数材料的绝缘体层与本体层分离的半导体层。 制造方法包括修改介电层的区域以具有较低的介电常数。

公开(公告)号：US20070166890A1

公开(公告)日：2007-07-19

申请号：US11335763

申请日：2006-01-19

Applicant: Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

Inventor： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

IPC: H01L21/84

CPC classification number: H01L29/66742 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687

Abstract: In a first aspect, a first method of manufacturing a PFET on a substrate is provided. The first method includes the steps of (1) forming a gate channel region of the PFET having a first thickness on the substrate; and (2) forming at least one composite source/drain diffusion region of the PFET having a second thickness greater than the first thickness on the substrate. The at least one composite source/drain diffusion region is adapted to cause a strain in the gate channel region. Further, significantly all of the at least one composite source/drain diffusion region is below a bottom surface of a gate of the PFET. Numerous other aspects are provided.

Abstract translation: 在第一方面中，提供了在衬底上制造PFET的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成具有第一厚度的PFET的栅极沟道区; 和（2）在衬底上形成具有大于第一厚度的第二厚度的PFET的至少一个复合源极/漏极扩散区域。 至少一个复合源极/漏极扩散区域适于在栅极沟道区域引起应变。 此外，显着地所有的至少一个复合源极/漏极扩散区域在PFET的栅极的底表面之下。 提供了许多其他方面。

公开(公告)号：US20070122982A1

公开(公告)日：2007-05-31

申请号：US11657154

申请日：2007-01-24

Applicant: Victor Chan ,  Yong Lee ,  Haining Yang

Inventor： Victor Chan ,  Yong Lee ,  Haining Yang

IPC: H01L21/8234

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/665

Abstract: A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.

Abstract translation: 提供了制造半导体器件结构的方法。 在这种方法中，p型场效应晶体管（PFET）和n型场效应晶体管（NFET），NFET和PFET中的每一个具有设置在基板的单晶半导体区域中的导电沟道。 可以形成具有第一大小的压应力的应力膜覆盖在PFET和NFET上。 期望地，形成掩模以在暴露NFET的同时覆盖PFET，之后理想地，覆盖NFET的应力膜的一部分经受离子注入，而掩模保护覆盖PFET的应力膜的另一部分与 离子注入。 然后可以对衬底进行退火，因此期望地，应力膜的注入部分的压缩应力通过退火从第一量级大大降低。 以这种方式，覆盖NFET的应力膜的注入部分期望地将大大减小的压缩应力，零应力和拉伸应力中的一个施加到NFET的传导通道。 应力膜的另一部分可以继续将第一大小的压应力赋予PFET的传导通道。