公开(公告)号：US11737260B2

公开(公告)日：2023-08-22

申请号：US17034727

申请日：2020-09-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Wen Su ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Chia-En Huang

IPC分类号： H01L21/321 ,  H10B20/20 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06

CPC分类号： H10B20/20 ,  H01L29/045 ,  H01L29/0692 ,  H01L29/66545

摘要： A memory device includes a substrate, an active region, a first gate structure, a second gate structure, a first word line, and a second word line. The active region protrudes from a top surface of the substrate. The active region has at least one ring structure, in which when viewed from above, the ring structure has a first linear portion, a second linear portion, a first curved portion, and a second curved portion, the first curved portion connects first sides of the first and second linear portions, and the second curved portion connects second sides of the first and second linear portions. The first gate structure and the second gate structure are over the substrate and cross the active region. The first word line and the second word line are electrically connected to the first gate structure and the second gate structure, respectively.

公开(公告)号：US11600623B2

公开(公告)日：2023-03-07

申请号：US16657421

申请日：2019-10-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H01L27/11 ,  G11C11/412 ,  G06F30/30

摘要： Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.

公开(公告)号：US11527539B2

公开(公告)日：2022-12-13

申请号：US16888269

申请日：2020-05-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

IPC分类号： G11C7/12 ,  H01L27/11 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

摘要： A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.

公开(公告)号：US20220359536A1

公开(公告)日：2022-11-10

申请号：US17873626

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H01L27/11 ,  G11C11/412 ,  G06F30/30

摘要： Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

公开(公告)号：US11475942B2

公开(公告)日：2022-10-18

申请号：US17154608

申请日：2021-01-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/419

摘要： Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US20220301646A1

公开(公告)日：2022-09-22

申请号：US17833419

申请日：2022-06-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Wen Su ,  Shih-Hao Lin ,  Jui-Lin Chen ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC分类号： G11C17/16 ,  H01L27/112 ,  H01L29/06 ,  H01L21/265

摘要： The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.

公开(公告)号：US11450673B2

公开(公告)日：2022-09-20

申请号：US16945146

申请日：2020-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786

摘要： A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US11387240B2

公开(公告)日：2022-07-12

申请号：US16854772

申请日：2020-04-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC分类号： H01L27/11 ,  G11C11/412 ,  H01L29/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768

摘要： An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

公开(公告)号：US20220181332A1

公开(公告)日：2022-06-09

申请号：US17682061

申请日：2022-02-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC分类号： H01L27/11 ,  H01L29/417 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40

摘要： A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

公开(公告)号：US20210398588A1

公开(公告)日：2021-12-23

申请号：US17154608

申请日：2021-01-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC分类号： G11C11/412 ,  G11C11/419 ,  H01L27/11

摘要： Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.