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    Logic compatible RRAM structure and process
    61.
    发明授权
    Logic compatible RRAM structure and process 有权

    公开(公告)号：US10158070B2

    公开(公告)日：2018-12-18

    申请号：US15852333

    申请日：2017-12-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

    IPC: H01L45/00

    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

    Resistance variable memory structure
    62.
    发明授权
    Resistance variable memory structure 有权

    公开(公告)号：US10050197B2

    公开(公告)日：2018-08-14

    申请号：US15614004

    申请日：2017-06-05

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuo-Chi Tu ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Yu-Wen Liao ,  Chin-Chieh Yang ,  Wen-Ting Chu

    IPC: H01L45/00

    Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer.

    Resistive random access memory and manufacturing method thereof
    64.
    发明授权
    Resistive random access memory and manufacturing method thereof 有权

    公开(公告)号：US09608204B2

    公开(公告)日：2017-03-28

    申请号：US14021364

    申请日：2013-09-09

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Po-Hao Lee ,  Chung-Cheng Chou ,  Wen-Ting Chu

    IPC: H01L45/00

    CPC classification number: H01L45/1608 ,  H01L45/08 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683

    Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.

    Process-compatible decoupling capacitor and method for making the same
    65.
    发明授权
    Process-compatible decoupling capacitor and method for making the same 有权
    过程兼容去耦电容及其制作方法

    公开(公告)号：US09583556B2

    公开(公告)日：2017-02-28

    申请号：US14552117

    申请日：2014-11-24

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Kuo-Chi Tu ,  Wen-Ting Chu

    IPC: H01L21/8242 ,  H01L49/02 ,  H01L45/00 ,  H01L21/8239 ,  H01L27/06 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L21/8239 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/16 ,  H01L45/1675

    Abstract: Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

    Abstract translation: 提供一种形成去耦电容器件及其装置的方法。 去耦电容器装置包括在沉积工艺中沉积的第一电介质层部分，其沉积用于非易失性存储单元的第二电介质层部分。 使用单个掩模对两个部分进行图案化。 还提供了片上系统（SOC）器件，SOC包括位于单个金属间介电层中的RRAM单元和去耦电容器。 还提供了一种形成工艺兼容去耦电容器的方法。 该方法包括图案化顶部电极层，绝缘层和底部电极层，以形成非易失性存储元件和去耦电容器。

    Method for operating RRAM memory
    66.
    发明授权
    Method for operating RRAM memory 有权
    操作RRAM内存的方法

    公开(公告)号：US09424917B2

    公开(公告)日：2016-08-23

    申请号：US13788063

    申请日：2013-03-07

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Yang Chang ,  Wen-Ting Chu ,  Chia-Fu Lee

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0097 ,  G11C2213/79

    Abstract: Methods for operating memory are disclosed. A method includes applying a select word line voltage to a word line node of a first resistive random access memory (RRAM) cell; applying a first programming voltage to a source line node of the first RRAM cell; and setting the first RRAM cell comprising applying a second programming voltage to a bit line node of the first RRAM cell. The first programming voltage is greater than zero volts, and the second programming voltage is greater than the first programming voltage. Other disclosed methods include concurrently setting and resetting RRAM cells.

    Abstract translation: 公开了操作存储器的方法。 一种方法包括：将选择字线电压施加到第一电阻随机存取存储器（RRAM）单元的字线节点; 将第一编程电压施加到所述第一RRAM单元的源极线节点; 以及设置所述第一RRAM单元包括将第二编程电压施加到所述第一RRAM单元的位线节点。 第一编程电压大于零伏，第二编程电压大于第一编程电压。 其他公开的方法包括同时设置和重置RRAM单元。

    Resistive Memory Cell Array With Top Electrode Bit Line
    69.
    发明申请
    Resistive Memory Cell Array With Top Electrode Bit Line 有权
    电阻位线电阻记忆单元阵列

    公开(公告)号：US20150155488A1

    公开(公告)日：2015-06-04

    申请号：US14617499

    申请日：2015-02-09

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Yang Chang ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Hsia-Wei Chen ,  Yu-Wen Liao ,  Chin-Chieh Yang

    IPC: H01L45/00

    CPC classification number: H01L45/1666 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  Y10S438/90

    Abstract: A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.

    Abstract translation: 用于在存储器阵列内形成电阻存储单元的方法包括在形成在衬底上的第一金属层上形成图案化的阻挡层，并形成底部电极作为图案化阻挡层的特征。 该方法还包括形成电阻存储层。 电阻性存储层包括金属氧化物层和顶部电极层。 该方法还包括图案化电阻性存储层，使得顶部电极层用作存储器阵列内的位线和电阻存储器单元的顶部电极。

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