公开(公告)号：US20240324478A1

公开(公告)日：2024-09-26

申请号：US18732725

申请日：2024-06-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10N70/063 ,  H10B63/30 ,  H10N70/231 ,  H10N70/826

Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

公开(公告)号：US12082421B2

公开(公告)日：2024-09-03

申请号：US18324245

申请日：2023-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tzu-Yu Chen ,  Sheng-Hung Shih ,  Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu

IPC: H01L21/00 ,  H01L21/02 ,  H01L49/02 ,  H10B53/30

CPC classification number: H10B53/30 ,  H01L21/0234 ,  H01L21/02356 ,  H01L28/60

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

公开(公告)号：US12069971B2

公开(公告)日：2024-08-20

申请号：US18313475

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hai-Dang Trinh ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin ,  Wen-Ting Chu

IPC: H10N70/00 ,  G06F12/02 ,  H10N70/20 ,  H10B63/00

CPC classification number: H10N70/801 ,  G06F12/0246 ,  H10N70/021 ,  H10N70/061 ,  H10N70/063 ,  H10N70/24 ,  H10N70/826 ,  H10N70/881 ,  H10N70/8833 ,  H10N70/8836 ,  H10B63/30 ,  H10N70/883

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes a first metal and a second metal. The first metal has a peak concentration at a first distance from the first electrode and the second metal has a peak concentration at a second distance from the first electrode. The first distance is different than the second distance.

公开(公告)号：US12057154B2

公开(公告)日：2024-08-06

申请号：US17370144

申请日：2021-07-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tzu-Yu Chen ,  Sheng-Hung Shih ,  Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu

IPC: G11C11/22 ,  G11C7/20

CPC classification number: G11C11/221 ,  G11C7/20

Abstract: A method for efficiently waking up ferroelectric memory is provided. A wafer is formed with a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of ferroelectric memory cells that constitute a ferroelectric memory array. Each of the ferroelectric memory cells is electrically connected to one of the first signal lines, one of the second signal lines and one of the third signal lines. Voltage signals are simultaneously applied to the first signal lines, the second signal lines and the third signal lines to induce occurrence of a wake-up effect in the ferroelectric memory cells.

公开(公告)号：US20230371396A1

公开(公告)日：2023-11-16

申请号：US18357332

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tong-Chern Ong ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Kuei-Hung Shen ,  Kuo-Yuan Tu ,  Sheng-Huang Huang

IPC: H10N50/80 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/011 ,  H10N70/20 ,  H10N70/021 ,  H10N70/063 ,  H10N70/826 ,  H10N70/8833

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. The bottom electrode has a first thickness along an outermost edge and a second thickness between the outermost edge and a lateral center of the bottom electrode. The first thickness is larger than the second thickness. A data storage structure is over the bottom electrode and a top electrode is over the data storage structure.

公开(公告)号：US20230276721A1

公开(公告)日：2023-08-31

申请号：US18313475

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hai-Dang Trinh ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin ,  Wen-Ting Chu

IPC: H10N70/00 ,  G06F12/02 ,  H10N70/20

CPC classification number: H10N70/801 ,  G06F12/0246 ,  H10N70/021 ,  H10N70/24 ,  H10N70/061 ,  H10N70/063 ,  H10N70/826 ,  H10N70/881 ,  H10N70/8833 ,  H10N70/8836 ,  H10B63/30

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes a first metal and a second metal. The first metal has a peak concentration at a first distance from the first electrode and the second metal has a peak concentration at a second distance from the first electrode. The first distance is different than the second distance.

公开(公告)号：US20220293681A1

公开(公告)日：2022-09-15

申请号：US17829572

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L27/11507 ,  H01L45/00 ,  H01L43/12 ,  H01L27/22

Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.

公开(公告)号：US20220157889A1

公开(公告)日：2022-05-19

申请号：US17589278

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Chieh Yang ,  Hsia-Wei Chen ,  Chih-Yang Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/78

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

公开(公告)号：US20220093849A1

公开(公告)日：2022-03-24

申请号：US17537830

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H01L43/02 ,  H01L23/538 ,  H01L43/12 ,  H01L27/22 ,  H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L43/08

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

公开(公告)号：US20210296401A1

公开(公告)日：2021-09-23

申请号：US17342731

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L27/11507 ,  H01L45/00 ,  H01L43/12 ,  H01L27/22

Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.