公开(公告)号：US20220246190A1

公开(公告)日：2022-08-04

申请号：US17679601

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan Hatcher ,  Jorge A. Kittl

IPC: G11C11/16 ,  G06N3/063 ,  G06F7/50 ,  H01L43/06 ,  H01L43/04 ,  H01L43/10 ,  H01L43/08

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.

公开(公告)号：US11290110B2

公开(公告)日：2022-03-29

申请号：US15886179

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H03K19/21 ,  G06N3/063 ,  H03K19/18

Abstract: A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

公开(公告)号：US11217392B2

公开(公告)日：2022-01-04

申请号：US16417346

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Palle

IPC: H01L41/083 ,  H01G4/12 ,  H01L29/51 ,  H01L29/78 ,  H01G4/008

Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

公开(公告)号：US11101320B2

公开(公告)日：2021-08-24

申请号：US16850691

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G11C11/15 ,  H01L27/22 ,  G11C11/16 ,  G11C13/00 ,  H01F10/32 ,  H01L43/02 ,  H01L27/24

Abstract: A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

公开(公告)号：US20210133544A1

公开(公告)日：2021-05-06

申请号：US16849638

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Dharmendar Palle ,  JoonGoo Hong

IPC: G06N3/063

Abstract: A method and system are provided. The method includes mapping a binary matrix to an undirected graph form, applying a two-way graph partition algorithm to the mapped binary matrix that minimizes edge cuts between partitions in the mapped binary matrix, applying a greedy algorithm recursively to find a set of row or column permutations that maximizes a transfer of non-zeros from sparse blocks to nonsparse blocks, and sparsifying or densifying the binary matrix according to the applied greedy algorithm.

公开(公告)号：US20210118950A1

公开(公告)日：2021-04-22

申请号：US16850691

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: H01L27/22 ,  H01L27/24 ,  G11C11/16 ,  H01L43/02 ,  G11C13/00 ,  H01F10/32

Abstract: A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

公开(公告)号：US20210117769A1

公开(公告)日：2021-04-22

申请号：US17133427

申请日：2020-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/063 ,  G06N3/04 ,  H01L27/112 ,  H01L27/11556 ,  G06N3/08

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US20210056401A1

公开(公告)日：2021-02-25

申请号：US17094356

申请日：2020-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/808 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US10909449B2

公开(公告)日：2021-02-02

申请号：US15678050

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/063 ,  G06N3/04 ,  H01L27/112 ,  H01L27/11556 ,  G06N3/08 ,  G11C13/00

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US10861950B2

公开(公告)日：2020-12-08

申请号：US16121427

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/118

Abstract: A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.