公开(公告)号：US12100634B2

公开(公告)日：2024-09-24

申请号：US17500026

申请日：2021-10-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L23/291 ,  H01L23/3128 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/3512

Abstract: The present application discloses a semiconductor device with a re-fill layer. The semiconductor device includes a chip stack including a first base die; a first stacked die positioned on a front surface of the first base die; and a re-fill layer positioned on a sidewall of the stacked die. The re-fill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide, or hafnium oxide.

公开(公告)号：US11935831B2

公开(公告)日：2024-03-19

申请号：US17511101

申请日：2021-10-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L23/528 ,  H01L21/76838 ,  H01L23/49816 ,  H01L24/14

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a first semiconductor structure; and forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, a plurality of first connecting contacts in the first connecting insulating layer, and a plurality of first supporting contacts in the first connecting insulating layer.

公开(公告)号：US11901344B2

公开(公告)日：2024-02-13

申请号：US17506706

申请日：2021-10-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/49 ,  H01L25/10 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/50 ,  H01L23/5384 ,  H01L2225/06541

Abstract: A manufacturing method of a semiconductor package is provided as follows. A semiconductor die is provided, wherein the semiconductor die comprises a semiconductor substrate, an interconnection layer and a through semiconductor via, the interconnection layer is disposed on an active surface of the semiconductor substrate, the through semiconductor via penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate. An encapsulant is provided to laterally encapsulate the semiconductor die. A through encapsulant via penetrating through the encapsulant is formed.

公开(公告)号：US11876063B2

公开(公告)日：2024-01-16

申请号：US17462330

申请日：2021-08-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/05 ,  H01L2224/02372 ,  H01L2224/05093 ,  H01L2224/32012 ,  H01L2224/33104

Abstract: A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

公开(公告)号：US11765882B2

公开(公告)日：2023-09-19

申请号：US17520519

申请日：2021-11-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L21/76 ,  H10B12/00 ,  G11C5/06 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B12/05 ,  G11C5/063 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/31 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50 ,  H10B43/27 ,  H10B43/40

Abstract: The present application discloses a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes providing a substrate comprising a center area and a peripheral area surrounding the center area, forming a first gate stack on the peripheral area and having a top surface, and forming an active column in the center area and having a top surface at a same vertical level as the top surface of the first gate stack.

公开(公告)号：US11742242B2

公开(公告)日：2023-08-29

申请号：US17584383

申请日：2022-01-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih ,  Sheng-Fu Huang

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76865 ,  H01L23/481 ,  H01L2224/08145 ,  H01L2225/06541

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. A first device structure layer is between a first substrate and a second substrate. A second device structure layer is between the second substrate and the first device structure layer. A first dielectric layer is between the first and second device structure layers. A second dielectric layer is on the second substrate. A through-silicon via (TSV) structure is in the second dielectric layer, the second substrate, the second device structure layer and the first dielectric layer. A connection pad is at the surface of the second dielectric layer and connected to the TSV structure. A first liner is between the TSV structure and the second dielectric layer, the second substrate and the second device structure layer. A second liner is between the top of the
TSV structure and the second dielectric layer and a part of the second substrate.

公开(公告)号：US11658070B2

公开(公告)日：2023-05-23

申请号：US17643182

申请日：2021-12-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Shing-Yih Shih

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/83896 ,  H01L2224/83931

Abstract: A method of forming a semiconductor structure includes following steps. A first wafer is bonded to a second wafer, in which the first wafer includes a first substrate and a first conductive pad above a first surface of the first substrate, and the second wafer comprises a second substrate and a second conductive pad above a second surface of the second substrate. A mask layer is formed above the first substrate. The mask layer and the first substrate are etched to form a first opening in the first substrate. A sacrificial spacer is formed in the first substrate at a sidewall of the first opening. The first conductive pad is etched to form a second opening communicated to the first opening. A conductive material is filled in the first opening and the second opening to form a conductive structure interconnecting the first and second conductive pads.

公开(公告)号：US11646299B2

公开(公告)日：2023-05-09

申请号：US17643593

申请日：2021-12-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L25/10 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/14 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/14104 ,  H01L2224/14517 ,  H01L2224/95001 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/35121

Abstract: A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.

公开(公告)号：US11621341B2

公开(公告)日：2023-04-04

申请号：US16820273

申请日：2020-03-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first region, and a first transistor positioned in the first region. The first transistor includes a first bottom gate structure positioned on the substrate, a first channel layer positioned on the first bottom gate structure, a first top gate structure positioned on the first channel layer, and two first source/drain regions positioned on two sides of the first channel layer.

公开(公告)号：US11605612B2

公开(公告)日：2023-03-14

申请号：US17520526

申请日：2021-11-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

Abstract: The present disclosure provides a method of manufacturing a semiconductor package assembly. The method includes steps of providing a plurality of first dies arranged horizontally; forming a redistribution layer on the first dies and the first insulative material, wherein the redistribution layer is divided into a first segment and a second segment electrically isolated from the first segment; mounting a plurality of second dies on the first segment of the redistribution layer; depositing a second insulative layer on the second dies and the redistribution layer; and forming a plurality of conductive plugs penetrating through the second insulative material and contacting the second segment of the redistribution layer.