公开(公告)号：US07361539B2

公开(公告)日：2008-04-22

申请号：US11383560

申请日：2006-05-16

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L29/7842

摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

摘要翻译： 提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。 包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。 第一和第二栅极导体是在第一和第二沟道区两者上延伸的单个细长导电构件的部分。 第一应力膜覆盖第一FET，第一应力膜将具有第一值的应力施加到第一沟道区。 第二应力膜覆盖第二FET，第二应力膜向第二沟道区施加具有第二值的应力。 第二个值与第一个值大不相同。 此外，第一和第二应力膜在共同边界处彼此邻接并且在共同边界处呈现基本上共平面的主表面。

公开(公告)号：US20080001182A1

公开(公告)日：2008-01-03

申请号：US11427495

申请日：2006-06-29

申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L27/148

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

摘要翻译： 本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。 具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着 第二，不同组的等效晶面。 这种附加表面可以通过晶体蚀刻容易地形成。 此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。 这样的应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

公开(公告)号：US07307323B2

公开(公告)日：2007-12-11

申请号：US11369409

申请日：2006-03-07

申请人： Hung Y. Ng ,  Haining S. Yang

发明人： Hung Y. Ng ,  Haining S. Yang

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/0629 ,  H01L29/6656

摘要： An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

摘要翻译： 覆盖晶体管栅极叠层的侧壁并且沿晶体管栅极堆叠的基极的衬底的一部分覆盖的耐蚀刻衬里。 衬垫防止在栅极堆叠的侧壁上形成硅化物，这可能产生电短路，并且确定在晶体管栅极堆叠的基极处的衬底内的源极和漏极区域内的硅化物形成的位置。 衬套还覆盖阻止在电阻器栅极叠层内或邻近电阻器栅叠层形成硅化物的电阻器栅极堆叠。

公开(公告)号：US06906360B2

公开(公告)日：2005-06-14

申请号：US10605134

申请日：2003-09-10

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer O. Dokumaci ,  Haining S. Yang

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer O. Dokumaci ,  Haining S. Yang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/73

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

摘要： A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

摘要翻译： 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

公开(公告)号：US08853746B2

公开(公告)日：2014-10-07

申请号：US11427495

申请日：2006-06-29

申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L27/148 ,  H01L29/66 ,  H01L29/165 ,  H01L29/786 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L29/04 ,  H01L29/10 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

摘要翻译： 本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。 具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着 第二，不同组的等效晶面。 这种附加表面可以通过晶体蚀刻容易地形成。 此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。 这种应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

公开(公告)号：US08765558B2

公开(公告)日：2014-07-01

申请号：US13427237

申请日：2012-03-22

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/823878 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.

公开(公告)号：US08629506B2

公开(公告)日：2014-01-14

申请号：US12407011

申请日：2009-03-19

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L21/70

CPC分类号： H01L21/823878 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.

摘要翻译： CMOS结构和用于制造CMOS结构的方法包括位于半导体衬底内的位于第一极性的第一有源区上的第一栅极和位于不同于第一极性的第二极性的第二有源区上的第二栅极。 第一有源区和第二有源区被隔离区隔开。 第一栅极和第二栅极是共线的，面向端壁终止在隔离区上。 面对的端壁不具有相邻或邻接的间隔件，尽管第一栅极和第二栅极的侧壁都是。 可以使用顺序替换栅极方法来制造CMOS结构。

公开(公告)号：US08587062B2

公开(公告)日：2013-11-19

申请号：US11690975

申请日：2007-03-26

申请人： Jack A. Mandelman ,  Haining S. Yang

发明人： Jack A. Mandelman ,  Haining S. Yang

IPC分类号： H01L27/12

CPC分类号： H01L29/78615

摘要： A field effect transistor (FET) with an adjacent body contact, a SOI IC with circuits including the FETs and a method of fabricating the ICs. Device islands are formed in the silicon surface layer of a SOI wafer. Gates are defined on the wafer. Body contacts are formed in a perimeter conductive region adjacent to the gates. The body contacts may be either a silicide strap along the gate sidewall at one side of the FET or a separate contact separated from the gate by a dielectric stripe at one side of the FET. Separate contacts may be connected to a bias supply.

摘要翻译： 具有相邻体接触的场效应晶体管（FET），具有包括FET的电路的SOI IC和制造IC的方法。 器件岛形成在SOI晶片的硅表面层中。 盖子被定义在晶圆上。 主体触点形成在与栅极相邻的周边导电区域中。 主体触点可以是沿FET的一侧的栅极侧壁的硅化物带或通过FET一侧的介电条与栅极分开的单独触点。 单独的触点可能连接到偏置电源。

公开(公告)号：US20120214301A1

公开(公告)日：2012-08-23

申请号：US13453165

申请日：2012-04-23

申请人： Deok-Kee Kim ,  Ahmet S. Ozcan ,  Haining S. Yang

发明人： Deok-Kee Kim ,  Ahmet S. Ozcan ,  Haining S. Yang

IPC分类号： H01L21/28

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

摘要翻译： 电熔丝结构和方法具有阳极; 熔丝连接（熔丝连接的第一端连接到阳极）; 阴极（与第一端相对的熔断体的第二端连接到阴极）; 和熔丝链上的硅化物层。 硅化物层具有邻近阳极的第一硅化物区域和与阴极相邻的第二硅化物区域。 第二硅化物区域包括不包含在第一硅化物区域内的杂质。 此外，第一硅化物区域比第二硅化物区域薄。

公开(公告)号：US08093644B2

公开(公告)日：2012-01-10

申请号：US12350432

申请日：2009-01-08

申请人： Haining S. Yang

发明人： Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L51/0558 ,  B82Y10/00 ,  G11C13/025 ,  G11C16/0416 ,  G11C2213/17 ,  H01L21/28273 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/939

摘要： A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.

摘要翻译： 一种基于碳纳米管的存储器件包括一组具有不同直径的三个同心碳纳米管。 选择三个同心碳纳米管的直径使得内部碳纳米管是半导体的，并且在相邻的碳纳米管之间发生壳内电子传递。 对内部碳纳米管进行源极和漏极接触，并对外部碳纳米管进行栅极接触。 基于碳纳米管的存储器件通过在壳碳纳米管中通过壳电子传输存储电子或空穴进行编程。 检测由于中间壳中的电荷导致的内部碳纳米管的电导率的变化，以确定中间碳纳米管的电荷状态。 因此，基于碳纳米管的存储装置以电荷的形式将信息存储在中间碳纳米管中。