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    Performance of additional refresh operations during self-refresh mode
    64.
    发明授权
    Performance of additional refresh operations during self-refresh mode 有权

    公开(公告)号：US09721640B2

    公开(公告)日：2017-08-01

    申请号：US15184944

    申请日：2016-06-16

    Applicant: Intel Corporation

    Inventor： Kuljit S. Bains ,  Shay Fux ,  John B. Halbert

    IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074

    CPC classification number: G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

    Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

    EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DYNAMIC RANDOM ACCESS MEMORY (DRAM) ERROR CORRECTION CODE (ECC)
    66.
    发明申请
    EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DYNAMIC RANDOM ACCESS MEMORY (DRAM) ERROR CORRECTION CODE (ECC) 有权
    从片上动态随机访问存储器（DRAM）提取选择信息错误修正代码（ECC）

    公开(公告)号：US20160283318A1

    公开(公告)日：2016-09-29

    申请号：US14670413

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Debaleena Das ,  Bill Nale ,  Kuljit S. Bains ,  John B. Halbert

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

    Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

    Abstract translation: 存储器子系统中的错误校正包括在执行内部错误检测和校正之后产生内部校验位的存储器件，以及向内存控制器提供内部校验位。 存储器件执行内部错误检测以响应于来自存储器控制器的读取请求来检测读取数据中的错误。 如果在读取的数据中检测到错误，则存储器件选择性地执行内部纠错。 在执行内部错误检测和校正之后，存储器件产生指示读取数据的错误向量的校验位，并且响应于读取请求将校验位与读取的数据提供给存储器控制器。 存储器控制器可以将校验位应用于存储器件外部的纠错。

    METHOD, APPARATUS AND SYSTEM FOR RESPONDING TO A ROW HAMMER EVENT
    67.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR RESPONDING TO A ROW HAMMER EVENT 有权
    方法，设备和系统，用于响应一个ROW HAMMER事件

    公开(公告)号：US20160225434A1

    公开(公告)日：2016-08-04

    申请号：US15011286

    申请日：2016-01-29

    Applicant: Intel Corporation

    Inventor： John B. Halbert ,  Kuljit S. Bains

    IPC: G11C11/406 ,  G11C7/10 ,  G06F12/06

    CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

    Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

    Abstract translation: 促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。 在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新 设备。 在这样的命令之前，存储器设备从存储器控制器服务另一命令。 在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。

    DISABLING A COMMAND ASSOCIATED WITH A MEMORY DEVICE
    68.
    发明申请
    DISABLING A COMMAND ASSOCIATED WITH A MEMORY DEVICE 有权
    禁用与存储设备相关的命令

    公开(公告)号：US20150277790A1

    公开(公告)日：2015-10-01

    申请号：US14230338

    申请日：2014-03-31

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Kuljit S. Bains

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

    Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

    Abstract translation: 在一个实施例中，存储器设备可以包含设备处理逻辑和模式寄存器。 模式寄存器可以是可以指定存储器件的操作模式的寄存器。 模式寄存器中的字段可以保存可以指示与存储器设备相关联的命令是否被禁用的值。 该值可以保持在现场，直到存储器件被上电或复位为止。 设备处理逻辑可以获取命令的实例。 设备处理逻辑可以基于模式寄存器保持的值来确定该命令是否被禁用。 如果设备处理逻辑确定该命令被禁用，则设备处理逻辑可能不执行该命令的实例。 如果设备处理逻辑确定命令未被禁止，则设备处理逻辑可以执行该命令的实例。

    Row hammer monitoring based on stored row hammer threshold value
    69.
    发明授权
    Row hammer monitoring based on stored row hammer threshold value 有权
    行锤监测基于存储的行锤阈值

    公开(公告)号：US09032141B2

    公开(公告)日：2015-05-12

    申请号：US13690523

    申请日：2012-11-30

    Applicant: Intel Corporation

    Inventor： Kuljit S. Bains ,  John B. Halbert

    IPC: G06F12/00 ,  G11C11/406 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/50 ,  G06F13/16

    CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012

    Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

    Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定对存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

    ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE
    70.
    发明申请
    ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE 有权
    访问存储在命令/地址寄存器设备中的数据

    公开(公告)号：US20150089111A1

    公开(公告)日：2015-03-26

    申请号：US14560976

    申请日：2014-12-04

    Applicant: Intel Corporation

    Inventor： Kuljit S. Bains ,  Klaus J. Ruff ,  George Vergis ,  Suneeta Sah

    IPC: G06F13/28 ,  G06F13/16

    CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

    Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

    Abstract translation: 通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。 寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。 主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。 然后主机处理器从存储器件的寄存器读取信息。

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