公开(公告)号：US10522207B2

公开(公告)日：2019-12-31

申请号：US15665143

申请日：2017-07-31

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Shay Fux ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

公开(公告)号：US09721640B2

公开(公告)日：2017-08-01

申请号：US15184944

申请日：2016-06-16

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Shay Fux ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.