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    Apparatus, system and method to detect and improve an input clock performance of a memory device
    1.
    发明授权
    Apparatus, system and method to detect and improve an input clock performance of a memory device 有权

    公开(公告)号：US12217787B2

    公开(公告)日：2025-02-04

    申请号：US17349854

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Arvind A. Kumar ,  James Alexander McCall ,  Bill H. Nale ,  John R. Goles ,  Dean-Dexter R. Eugenio

    IPC: G06F1/12 ,  G06F1/08 ,  G06F13/16 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093

    Abstract: A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

    Memory bus MR register programming process
    2.
    发明授权
    Memory bus MR register programming process 有权

    公开(公告)号：US10891243B2

    公开(公告)日：2021-01-12

    申请号：US16529700

    申请日：2019-08-01

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  John V. Lovelace ,  John R. Goles

    IPC: G06F13/36 ,  G06F13/16 ,  G06F1/10

    Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

    Reference voltage training per path for high speed memory signaling
    4.
    发明授权
    Reference voltage training per path for high speed memory signaling 有权

    公开(公告)号：US12204751B2

    公开(公告)日：2025-01-21

    申请号：US17359423

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Arvind Kumar ,  Dean-Dexter R. Eugenio ,  John R. Goles ,  Santhosh Muskula

    IPC: G06F3/06 ,  G06N20/00

    Abstract: In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.

    MEMORY DEVICE MANAGEABILITY BUS
    5.
    发明申请
    MEMORY DEVICE MANAGEABILITY BUS 有权

    公开(公告)号：US20210406206A1

    公开(公告)日：2021-12-30

    申请号：US17470278

    申请日：2021-09-09

    Applicant: Intel Corporation

    Inventor： George Vergis ,  John R. Goles

    IPC: G06F13/16

    Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to enumerate respective sideband addresses to ten or more memory devices, and provide bi-directional communication with an individual memory device of the ten or more memory devices with a particular sideband address enumerated to the individual memory device. Other embodiments are disclosed and claimed.

    Memory bus MR register programming process
    6.
    发明授权
    Memory bus MR register programming process 有权

    公开(公告)号：US10380043B2

    公开(公告)日：2019-08-13

    申请号：US15718346

    申请日：2017-09-28

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  John V. Lovelace ,  John R. Goles

    IPC: G06F13/36 ,  G06F13/16 ,  G06F1/10

    Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

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