公开(公告)号：US11620358B2

公开(公告)日：2023-04-04

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US10599592B2

公开(公告)日：2020-03-24

申请号：US16283597

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Pete D. Vogt

IPC: G06F1/18 ,  G11C5/06 ,  G06F13/16

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

公开(公告)号：US20190272173A1

公开(公告)日：2019-09-05

申请号：US16419483

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F9/30 ,  G06F9/50

Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

公开(公告)号：US09922725B2

公开(公告)日：2018-03-20

申请号：US15368402

申请日：2016-12-02

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  William K. Lui ,  David G. Ellis ,  David J. Zimmerman ,  Theodore Z. Schoenborn ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang

IPC: G11C29/44 ,  G11C29/36 ,  G11C29/18 ,  G11C29/16 ,  G11C29/12 ,  G11C29/00 ,  G06F11/27 ,  G06F11/263 ,  G11C29/38 ,  G11C29/10 ,  G11C29/20 ,  G11C11/406

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.

公开(公告)号：US09548137B2

公开(公告)日：2017-01-17

申请号：US14320164

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  William K. Lui ,  David G. Ellis ,  David J. Zimmerman ,  Theodore Z. Schoenborn ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang

IPC: G11C29/44 ,  G11C29/36 ,  G11C29/10 ,  G11C29/00 ,  G11C11/406 ,  G06F11/27 ,  G06F11/263

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.

Abstract translation: 根据本说明书，装置包括内部缺陷检测和修复电路，其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。 在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。 在识别一个或多个有缺陷的存储器单元时，内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储器单元。

公开(公告)号：US20190266219A1

公开(公告)日：2019-08-29

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F7/78 ,  G06F9/38 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US20190043570A1

公开(公告)日：2019-02-07

申请号：US15911350

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Christopher Connor

IPC: G11C13/00 ,  G11C11/408 ,  H03K19/0175 ,  G11C29/12 ,  G11C14/00 ,  G11C11/56

Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

公开(公告)号：US10014036B1

公开(公告)日：2018-07-03

申请号：US15393951

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kuan Zhou ,  Bruce Querbach ,  Li Pan

IPC: G11C11/24 ,  G11C5/02 ,  G11C7/10

Abstract: An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.

公开(公告)号：US09977075B1

公开(公告)日：2018-05-22

申请号：US15360899

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Rahul Khanna

IPC: G06Q10/06 ,  G06Q10/08 ,  G01R31/28 ,  G06F17/50

CPC classification number: G01R31/2851 ,  G01R31/2855 ,  G06F17/5036

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

公开(公告)号：US11264094B2

公开(公告)日：2022-03-01

申请号：US15911350

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Christopher Connor

IPC: G11C11/56 ,  G11C13/00 ,  G11C11/408 ,  H03K19/0175 ,  G11C14/00 ,  G11C29/12 ,  G11C7/16 ,  G11C7/06 ,  G11C27/00 ,  G11C29/02 ,  G11C29/04

Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.