公开(公告)号：US20150357331A1

公开(公告)日：2015-12-10

申请号：US14830182

申请日：2015-08-19

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Ali Khakifirooz ,  Theodorus E. Standaert

IPC: H01L27/092 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/00 ,  H01L28/40 ,  H01L28/60 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/267 ,  H01L29/66 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/8613

Abstract: A method of forming a semiconductor structure within a semiconductor substrate is provided. The method may include forming, on the substrate, a first group of fins associated with a first device; a second group of fins associated with a second device; and a third group of fins located between the first group of fins and the second group of fins, whereby the third group of fins are associated with a third device. A shallow trench isolation (STI) region is formed between the first and the second group of fins by recessing the third group of fins into an opening within the substrate, such that the recessed third group of fins includes a fin top surface that is located below a top surface of the substrate. The top surface of the substrate is substantially coplanar with a fin bottom surface corresponding to the first and second group of fins.

Abstract translation: 提供了一种在半导体衬底内形成半导体结构的方法。 该方法可以包括在衬底上形成与第一装置相关联的第一组翅片; 与第二装置相关联的第二组翅片; 以及第三组散热片，位于所述第一散热片组和所述第二组翅片之间，由此所述第三组散热片与第三装置相关联。 通过将第三组翅片凹入基板内的开口中，在第一和第二组翅片之间形成浅沟槽隔离（STI）区域，使得凹陷的第三组翅片包括位于下方的翅片顶表面 衬底的顶表面。 基板的顶表面与对应于第一组翅片和第二组翅片的翅片底面基本共面。

公开(公告)号：US20150145041A1

公开(公告)日：2015-05-28

申请号：US14087867

申请日：2013-11-22

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Lars Wolfgang Liebmann ,  Shom Ponoth ,  Balasubramanian Pranatharthiharan ,  Scott R. Stiffler

IPC: H01L23/50 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/743 ,  H01L21/76895 ,  H01L27/1211

Abstract: A substrate local interconnect structure and method is disclosed. A buried conductor is formed in the insulator region or on the semiconductor substrate. The buried conductor may be formed by metal deposition, doped silicon regions, or silciding a region of the substrate. Metal sidewall portions connect transistor contacts to the buried conductor to form interconnections without the use of middle-of-line (MOL) metallization and via layers.

Abstract translation: 公开了一种衬底局部互连结构和方法。 在绝缘体区域或半导体衬底上形成掩埋导体。 掩埋导体可以通过金属沉积，掺杂的硅区域或者沉积衬底的区域来形成。 金属侧壁部分将晶体管触点连接到掩埋导体以形成互连，而不使用中间线（MOL）金属化和通孔层。

公开(公告)号：US20150145008A1

公开(公告)日：2015-05-28

申请号：US14088473

申请日：2013-11-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Shom S. Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/538

CPC classification number: H01L21/823431 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/0629 ,  H01L28/90 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Spacer structures are formed around an array of disposable mandrel structures and above a doped semiconductor material portion. A sidewall image transfer process is employed to pattern an upper portion of the doped semiconductor material portion into an array of doped semiconductor fins. After formation of a dielectric material layer on the top surfaces and sidewall surfaces of the doped semiconductor fins, gate-level mandrel structures are formed to straddle multiple semiconductor fins. A conductive hole-containing structure is formed to laterally surround a plurality of gate-level mandrel structures, which is subsequently removed. A contact-level dielectric layer is formed over the conductive hole-containing structure and the plurality of doped semiconductor fins. The semiconductor fins function as a lower electrode of a fin capacitor, and the conductive hole-containing structure functions as an upper electrode of the fin capacitor.

Abstract translation: 间隔结构形成在一次性心轴结构的阵列周围并且在掺杂的半导体材料部分之上。 采用侧壁图像转移处理将掺杂半导体材料部分的上部图案化成掺杂半导体鳍片的阵列。 在掺杂半导体鳍片的顶表面和侧壁表面上形成介电材料层之后，形成跨越多个半导体鳍片的门级芯棒结构。 形成导电孔结构以横向围绕多个门级芯棒结构，随后将其移除。 在含导电孔的结构和多个掺杂的半导体鳍片之上形成接触电介质层。 半导体鳍片用作散热片电容器的下电极，并且导电孔结构用作散热片电容器的上电极。

公开(公告)号：US08912607B2

公开(公告)日：2014-12-16

申请号：US13789018

申请日：2013-03-07

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

IPC: H01L21/70 ,  H01L27/092 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

Abstract translation: 可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。 此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。 在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。 图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。 导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

公开(公告)号：US20140124863A1

公开(公告)日：2014-05-08

申请号：US13771255

申请日：2013-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim ,  Ramachandra Divakaruni

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.

Abstract translation: 公开了用于形成局部绝缘体上硅（SOI）finFET的方法和结构。 翅片形成在块状基底上。 氮化物间隔件保护翅片侧壁。 浅沟槽隔离区域沉积在鳍片上。 氧化过程导致氧气扩散通过浅沟槽隔离区域并进入下面的硅。 氧与硅反应形成氧化物，为散热片提供电气隔离。 浅沟槽隔离区域与布置在鳍片上的翅片和/或氮化物间隔物直接物理接触。 还公开了包括体型翅片，SOI型翅片和平面区域的结构。

公开(公告)号：US20140103404A1

公开(公告)日：2014-04-17

申请号：US13653658

申请日：2012-10-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ying Li ,  Ramachandra Divakaruni ,  Vijay Narayanan ,  Richard S. Wise

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L29/66553 ,  H01L21/28247 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66545

Abstract: After formation of source and drain regions and a planarization dielectric layer, a disposable gate structure is removed to form a gate cavity. A gate dielectric and a lower gate electrode are formed within the gate cavity. The lower gate electrode is vertically recessed relative to the planarization dielectric layer to form a recessed region. An inner dielectric spacer is formed within the recessed region by depositing a conformal dielectric layer and removing horizontal portions thereof by an anisotropic etch. An upper gate electrode is formed by depositing another conductive material within a remaining portion of the recessed region. A contact level dielectric layer is formed and contact structures are formed to the source and drain regions. The inner dielectric spacer prevents an electrical short between the gate electrode and a contact structure that partially overlies the gate electrode by overlay variations during lithographic processes.

Abstract translation: 在形成源极和漏极区域和平坦化介电层之后，去除一次性栅极结构以形成栅极腔。 栅极电介质和下栅电极形成在栅极腔内。 下栅电极相对于平坦化电介质层垂直凹入以形成凹陷区域。 通过沉积保形介电层并通过各向异性蚀刻去除其水平部分，在凹陷区域内形成内部电介质间隔物。 通过在凹陷区域的剩余部分内沉积另一种导电材料来形成上部栅极电极。 形成接触电介质层，并且在源区和漏区形成接触结构。 内部电介质间隔物通过在光刻工艺期间的重叠变化来防止栅极电极和部分地覆盖栅电极的接触结构之间的电短路。

公开(公告)号：US20130183805A1

公开(公告)日：2013-07-18

申请号：US13788980

申请日：2013-03-07

Applicant: International Business Machines Corporation

Inventor： Keith Kwong Hon Wong ,  Ramachandra Divakaruni ,  Roger A. Booth, JR.

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L27/10861 ,  H01L27/10867 ,  H01L29/945

Abstract: A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.

Abstract translation: 双节点介质沟槽电容器包括在沟槽中形成的一叠层。 层的堆叠包括从底部到顶部的第一导电层，第一节点电介质层，第二导电层，第二节点电介质层和第三导电层。 双节点介电沟槽电容器包括两个背对背电容器，其包括第一电容器和第二电容器。 第一电容器包括第一导电层，第一节点电介质层，第二导电层，第二电容器包括第二导电层，第二节点电介质层和第三导电层。 双节点介质沟槽电容器可以提供使用具有与第一和第二节点电介质层相当的组成和厚度的单节点电介质层的沟槽电容器的大约两倍的电容。

公开(公告)号：US10991635B2

公开(公告)日：2021-04-27

申请号：US16517568

申请日：2019-07-20

Applicant: International Business Machines Corporation

Inventor： Dale Curtis McHerron ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Ravi K. Bonam ,  Ramachandra Divakaruni ,  William J. Starke ,  Maryse Cournoyer

IPC: H01L23/538 ,  H01L23/13 ,  H01L27/24 ,  H01L23/532

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

公开(公告)号：US10741554B2

公开(公告)日：2020-08-11

申请号：US16292934

申请日：2019-03-05

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Sameer H. Jain ,  Viraj Y. Sardesai ,  Keith H. Tabakman

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/28 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

公开(公告)号：US10707224B2

公开(公告)日：2020-07-07

申请号：US15988828

申请日：2018-05-24

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L27/11568 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/40 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.