公开(公告)号：US20120181664A1

公开(公告)日：2012-07-19

申请号：US13264063

申请日：2010-04-14

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/06 ,  H01L21/308 ,  H01L29/24 ,  H01L29/16

CPC classification number: H01L31/0392 ,  H01L31/035281 ,  Y02E10/50

Abstract: The present invention proposes a strip plate structure and a method of manufacturing the same. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing, each of said strip plates including a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets, each strip sheet alternately abutting either the first surfaces or the second surfaces of two adjacent strip plates.

Abstract translation: 本发明提出一种带状板结构及其制造方法。 在一个实施例中，带状板结构包括带板阵列，其包括以预定方向排列的多个带状板，每个带状板包括面向带状板结构的一个侧面方向的第一表面和面向 所述带状板结构的基本相反的侧面方向; 以及多个条状片，​​每个条带交替地邻接两个相邻带状板的第一表面或第二表面。

公开(公告)号：US20120178232A1

公开(公告)日：2012-07-12

申请号：US13427257

申请日：2012-03-22

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L21/336

CPC classification number: H01L21/823425 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include or provide a field effect device that includes a spacer shaped contact via. The spacer shaped contact via comprises a spacer shaped annular contact via that is located surrounding and separated from an annular spacer shaped gate electrode at the center of which may be located a non-annular and non-spacer shaped second contact via. The annular gate electrode as well as the annular contact via and the non-annular contact via may be formed sequentially in a self-aligned fashion while using a single sacrificial mandrel layer.

Abstract translation: 半导体结构和制造半导体结构的方法包括或提供一种场效应器件，其包括间隔物形状的接触通孔。 间隔件形状的接触通孔包括间隔件形状的环形接触通孔，该环形接触通孔位于围绕环形间隔件形状的栅极电极的周围并与之隔开，该环形间隔件形状的栅电极可以位于非环形和非隔离形状的第二接触通孔中。 环形栅电极以及环形接触通孔和非环形接触通孔可以以自对准方式顺序地形成，同时使用单个牺牲心轴层。

公开(公告)号：US20120171842A1

公开(公告)日：2012-07-05

申请号：US13419927

申请日：2012-03-14

Applicant: Huilong Zhu ,  Jing Wang

Inventor： Huilong Zhu ,  Jing Wang

IPC: H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

Abstract translation: 提供了一种浅沟槽隔离结构，其包含第一浅沟槽隔离部分，其包括第一浅沟槽材料和包括第二浅沟槽材料的第二浅沟槽隔离部分。 在至少一个第二有效区域上的至少一个第一有效区域和第二双向应力上的第一双轴应力被分别操纵以通过选择第一和第二有源区域来增强至少一个第一和第二有源区域的中间部分中的载流子迁移率， 第二浅沟槽材料以及调节所述至少一个第一有源区域和所述至少一个第二有源区域的每个部分横向邻接的浅沟槽隔离材料的类型。

公开(公告)号：US20120168823A1

公开(公告)日：2012-07-05

申请号：US13377766

申请日：2011-04-25

Applicant: Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

Inventor： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

IPC: H01L29/26 ,  H01L21/66

CPC classification number: H01L21/823807 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823878 ,  H01L21/8258 ,  H01L29/66477

Abstract: The present application discloses a semiconductor device and a method for forming the same. The method comprises: providing a first semiconductor layer and forming a first STI in the first semiconductor layer; determining a selected region in the first semiconductor layer, and making a portion of the first semiconductor layer in the selected region recessed; and in the selected region, epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer. According to the present invention, a structure with a second semiconductor layer selectively epitaxially grown and embedded in the first semiconductor layer can be formed by a simple process, and defects generated during the epitaxial growth process can be further reduced.

Abstract translation: 本申请公开了一种半导体器件及其形成方法。 该方法包括：提供第一半导体层并在第一半导体层中形成第一STI; 确定所述第一半导体层中的选定区域，以及使所述选定区域中的所述第一半导体层的一部分凹陷; 并且在所选择的区域中，在第一半导体层上外延生长第二半导体层，其中第二半导体层的材料与第一半导体层的材料不同。 根据本发明，可以通过简单的工艺形成具有选择性地外延生长并嵌入第一半导体层中的第二半导体层的结构，并且可以进一步减少在外延生长工艺期间产生的缺陷。

公开(公告)号：US20120104513A1

公开(公告)日：2012-05-03

申请号：US13344955

申请日：2012-01-06

Applicant: Huilong Zhu ,  Qingqing Liang

Inventor： Huilong Zhu ,  Qingqing Liang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/42376 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/28132 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66613 ,  H01L29/7831

Abstract: The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.

Abstract translation: 金属氧化物半导体场效应晶体管（MOSFET）的栅极包括源极侧栅电极和漏极侧栅电极，在栅极中间附近彼此邻接。 在一个实施例中，源极侧栅极包括基于氧化硅的栅极电介质，漏极侧栅极包括高k栅极电介质。 源极栅电极提供高载流子迁移率，而漏极侧栅电极提供良好的短沟道效应和减小的栅极泄漏。 在另一个实施例中，源极栅极和漏极栅电极包括不同的高k栅极电介质堆叠和不同的栅极导体材料，其中源极侧栅电极具有远离带隙边缘的四分之一带隙的第一功函数和漏极 侧栅电极在带隙边缘附近具有第二功函数。

公开(公告)号：US20120104495A1

公开(公告)日：2012-05-03

申请号：US13144182

申请日：2011-03-04

Applicant: Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/6675 ,  H01L29/78603 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.

Abstract translation: 本申请公开了一种半导体结构及其制造方法。 根据本发明的半导体结构利用公共接触来调节阈值电压，该公共触点具有延伸到背栅极区域的源极或漏极区域之外的部分并且提供源极或漏极区域与背栅极的电接触 区域，这导致简单的制造过程，增加的集成水平和降低的制造成本。 此外，背栅结构的非对称设计进一步增加了阈值电压并提高了器件的性能。

公开(公告)号：US20120043624A1

公开(公告)日：2012-02-23

申请号：US13132535

申请日：2011-01-27

Applicant: Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

Inventor： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78654 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834

Abstract: An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.

Abstract translation: 公开了一种超薄体晶体管和制造超薄体晶体管的方法。 超薄体晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及半导体衬底中的栅极结构的任一侧上的源极区和漏极区; 其中栅极结构包括栅极电介质层，嵌入栅极电介质层中的栅极和栅极两侧的间隔物; 所述超薄体晶体管还包括：主体区域和位于所述栅极结构之下且位于阱区域中的掩埋绝缘区域; 主体区域和埋入绝缘区域的两端分别与源极区域和漏极区域连接; 并且身体区域通过身体区域下的埋入绝缘区域与阱区域中的其它区域隔离。 超薄体晶体管具有较薄的体区，从而降低了短沟道效应。 在与替换栅极工艺一起制造超薄体晶体管的方法中，掩埋绝缘区域的形成与栅极自对准，这降低了间隔物下的寄生电阻。

公开(公告)号：US20120038006A1

公开(公告)日：2012-02-16

申请号：US12937652

申请日：2010-07-25

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.

Abstract translation: 本申请公开了一种半导体器件，其包括由半导体衬底上的半导体层形成并具有垂直于半导体衬底的主表面的两个相对侧的半导体材料的鳍; 源极区域和漏极区域，设置在所述半导体衬底中，邻近所述鳍片的两端并被所述鳍片桥接; 设置在所述翅片的中央部的通道区域; 以及设置在鳍的一侧的栅极电介质和栅极导体的堆叠，其中栅极导体通过栅极电介质与沟道区隔离，并且其中栅极电介质和栅极导体的堆叠远离 翅片在平行于半导体衬底的主表面的方向上，并且通过绝缘层与半导体衬底绝缘。 半导体器件具有改善的短沟道效应和减小的寄生电容和电阻，这有助于改善电性能并且有助于晶体管的缩小。

公开(公告)号：US20120013009A1

公开(公告)日：2012-01-19

申请号：US12996721

申请日：2010-07-14

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76831 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor.

Abstract translation: 本发明公开了一种半导体结构及其制造方法。 半导体结构包括半导体衬底，连接到半导体衬底的局部互连结构以及电连接到局部互连结构的至少一个通孔堆叠结构，其中至少一个通孔堆叠结构包括具有上通孔和 下通孔，上通孔的宽度大于下通孔的宽度; 形成在靠近下通道的内壁的通孔间隔件; 覆盖通孔和通孔间隔物的表面的绝缘层; 形成在由所述绝缘层包围的空间内并且电连接到所述局部互连结构的导电插塞。 本发明可应用于半导体制造领域中的通孔叠层的制造。

公开(公告)号：US20110316080A1

公开(公告)日：2011-12-29

申请号：US12937486

申请日：2010-06-24

Applicant: Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

Inventor： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.

Abstract translation: 提供鳍式晶体管结构及其制造方法。 翅片晶体管结构包括形成在半导体衬底上的鳍片，其中在用作晶体管结构的沟道区域的鳍片的一部分和衬底之间形成绝缘材料，并且在半导体衬底的剩余部分之间形成体半导体材料 翅片和底物。 由此，可以在保持低成本，高热传递等优点的同时，减小电流泄漏。