公开(公告)号：US20180228046A1

公开(公告)日：2018-08-09

申请号：US15569807

申请日：2017-05-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jian XU ,  Pan LI ,  Jianbo XIAN

IPC: H05K7/14 ,  H01R12/70

CPC classification number: H05K7/1405 ,  G02F1/133308 ,  G02F1/13452 ,  G02F2001/133314 ,  H01R12/7076

Abstract: A fixing member, a device for mounting a circuit board, and a display apparatus so as to conveniently and firmly fix a PCB on the back plate of the back-light module are disclosed. The fixing member includes a supporting plate, a first clamping part fixedly arranged on an upper surface of the supporting plate, and a second clamping part facing the first clamping part. The first clamping part and the supporting plate form a first U-shape clamping groove. The second clamping part and the supporting plate form a second U-shape clamping groove. An opening of the first U-shape clamping groove faces an opening of the second U-shape clamping groove. The fixing member is used for fixing the circuit board on the back plate.

公开(公告)号：US20180203305A1

公开(公告)日：2018-07-19

申请号：US15741919

申请日：2017-04-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jianbo XIAN ,  Pan LI ,  Yong QIAO ,  Xinyin WU ,  Jian XU

IPC: G02F1/1343 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1362

CPC classification number: G02F1/134309 ,  G02F1/136209 ,  G02F1/136286 ,  G02F2201/121 ,  G02F2201/122 ,  G02F2201/123 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/127 ,  H01L29/78633 ,  H01L29/78669 ,  H01L29/7869

Abstract: Embodiments of the present disclosure provide an array substrate and a display device. The array substrate includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines crossing one another to bound pixel units and the pixel unites each including a pixel electrode and a thin film transistor, which includes a drain electrode, the array substrate further includes a common electrode line, the drain electrode includes an extension portion and the common electrode line and the extension portion form a light blocking structure together such that an orthographic projection of the light blocking structure on a plane where the pixel electrode is located is located near an edge of the pixel electrode. The array substrate provided by the present disclosure is applied to a display device.

公开(公告)号：US20180108676A1

公开(公告)日：2018-04-19

申请号：US15525622

申请日：2016-06-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hongfei CHENG ,  Jianbo XIAN ,  Pan LI ,  Xueguang HAO

IPC: H01L27/12 ,  H01L27/32 ,  H01L33/00 ,  H01L51/52 ,  G02F1/1362 ,  H01L29/786

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1222 ,  H01L27/3276 ,  H01L29/7869 ,  H01L33/0041 ,  H01L51/5284

Abstract: An array substrate, a method of manufacturing the same, and a display device are provided. In the array substrate of the present disclosure, the gate cutout is formed in the area where the gate line intersects the data line. The array substrate can reduce the coupling capacitance between the data line and the gate line. When the gate cutout extends beyond the area between the first thin film transistor and the second thin film transistor, the mutual interference between two thin film transistors of each pixel region can be further reduced.

公开(公告)号：US20170329164A1

公开(公告)日：2017-11-16

申请号：US15531814

申请日：2016-09-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xueguang HAO ,  Jianbo XIAN ,  Pan LI ,  Xinyin WU

IPC: G02F1/1368 ,  H01L27/12 ,  G02F1/1362 ,  H01L29/417 ,  H01L29/786 ,  G02F1/136

CPC classification number: G02F1/1368 ,  G02F1/1362 ,  G02F1/136286 ,  G02F2001/13606 ,  G02F2201/123 ,  G02F2201/50 ,  H01L27/124 ,  H01L29/08 ,  H01L29/41733 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78618

Abstract: A pixel structure, an array substrate and a display device is provided. The pixel structure includes a base substrate, and a gate layer and a source/drain layer arranged on the base substrate. An overlapping region is present between the gate layer and the source/drain layer, and the gate layer and/or the source/drain layer comprises a hollow structure located in the overlapping region.

公开(公告)号：US20170261801A1

公开(公告)日：2017-09-14

申请号：US15308400

申请日：2015-11-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenbo LI ,  Pan LI

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: G02F1/13624 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/122 ,  G02F2201/123 ,  G09G3/3648 ,  G09G2320/028

Abstract: An array substrate and a display apparatus are provided according to embodiments of the disclosure. A pixel unit includes a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode is connected to a drain of the first TFT, and the second sub-pixel electrode is connected to a drain of the second TFT, a resistance between a source of the first TFT and the data line connected to the first TFT is greater than a resistance between a source of the second TFT and the data line connected to the second TFT, and/or, a resistance between the drain of the first TFT and the first sub-pixel electrode is greater than a resistance between the drain of the second TFT and the second sub-pixel electrode.

公开(公告)号：US20170042022A1

公开(公告)日：2017-02-09

申请号：US14908815

申请日：2015-08-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xingchen SHANGGUAN ,  Pan LI ,  Jian XU ,  Yongda MA

IPC: H05K1/02 ,  G02F1/133

CPC classification number: H05K1/0242 ,  G02F1/13306 ,  G09G3/20 ,  G09G3/2096 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0252 ,  G09G2330/06 ,  G09G2370/08 ,  H05K1/0237 ,  H05K1/117 ,  H05K1/147 ,  H05K2201/10128 ,  H05K2201/10681

Abstract: The present invention discloses a circuit, a display substrate and a display device, the circuit comprises a plurality of circuit modules, distances of at least one circuit module from two circuit modules adjacent thereto are a first distance and a second distance, respectively, the first distance is smaller than the second distance, and the absolute value of the difference between the second distance and the first distance is not equal to an integer multiple of the first distance. In the present invention, distances of at least one circuit module from two circuit modules adjacent thereto satisfy the above specific condition, so that at least one circuit module can be prevented from being positioned at the middle position of the standing wave field between the two circuit modules adjacent thereto, therefore, interference of standing wave to transmission signals is reduced, and signal distortion and signal attenuation are alleviated.

Abstract translation: 本发明公开了一种电路，显示基板和显示装置，该电路包括多个电路模块，与其相邻的两个电路模块的至少一个电路模块的距离分别为第一距离和第二距离 距离小于第二距离，第二距离和第一距离之间的差的绝对值不等于第一距离的整数倍。 在本发明中，至少一个电路模块与其相邻的两个电路模块的距离满足上述特定条件，使得可以防止至少一个电路模块位于两个电路之间的驻波场的中间位置 因此，驻波对发送信号的干扰降低，信号失真和信号衰减减轻。

公开(公告)号：US20160370616A1

公开(公告)日：2016-12-22

申请号：US14771405

申请日：2015-04-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Hongfei CHENG ,  Jianbo XIAN ,  Yong QIAO ,  Yongchun LU ,  Wenbo LI ,  Pan LI

IPC: G02F1/1337 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1343

CPC classification number: G02F1/1337 ,  G02F1/133514 ,  G02F1/133707 ,  G02F1/133753 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133776 ,  G02F2001/134345 ,  G02F2201/121 ,  G02F2201/123

Abstract: The display panel includes multiple sub-pixel areas, a first substrate and a second substrate oppositely arranged to form a cell; and a liquid crystal layer disposed between the first substrate and the second substrate. The second substrate includes a first sub-pixel electrode and a second sub-pixel electrode disposed in each of multiple areas respectively corresponding to the plurality of sub-pixel areas, a protruded object is disposed in a gap between the first sub-pixel electrode and the second sub-pixel electrode, which are adjacent to each other and are respectively included in different sub-pixel areas, and a projection of the protruded object at least partially overlaps an area of the liquid crystal layer corresponding to the gap.

Abstract translation: 显示面板包括多个子像素区域，第一基板和第二基板，相对地布置成形成单元; 以及设置在第一基板和第二基板之间的液晶层。 第二基板包括分别对应于多个子像素区域的多个区域中的每一个中的第一子像素电极和第二子像素电极，突出物体设置在第一子像素电极与第二子像素电极之间的间隙中 所述第二子像素电极彼此相邻并且分别包括在不同的子像素区域中，并且所述突出物体的突起至少部分地与对应于所述间隙的所述液晶层的区域重叠。

公开(公告)号：US20160299392A1

公开(公告)日：2016-10-13

申请号：US14771748

申请日：2015-04-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hongfei CHENG ,  Jianbo XIAN ,  Yong QIAO ,  Yongchun LU ,  Jian XU ,  Yongda MA ,  Wenbo LI ,  Pan LI

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/134336 ,  G02F1/133707 ,  G02F1/134309 ,  G02F1/1362 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2201/121 ,  G02F2201/123

Abstract: A display substrate includes a first base substrate; a gate line, a data line and a common electrode line arranged on the first base substrate; a plurality of pixel units each including a first sub-pixel electrode, a second sub-pixel electrode, a first thin film transistor, a second thin film transistor and a third thin film transistor; and a charge adjustment-control line arranged on the first base substrate, where the charge adjustment-control line and the gate line are between the first sub-pixel electrode and the second sub-pixel electrode. The first thin film transistor is connected to the gate line, the data line and the first sub-pixel electrode; the second thin film transistor is connected to the gate line, the data line and the second sub-pixel electrode; the third thin film transistor is connected to the charge adjustment control line, the first sub-pixel electrode and the common electrode line.

Abstract translation: 显示基板包括：第一基底; 布线在第一基底上的栅极线，数据线和公共电极线; 多个像素单元，每个像素单元包括第一子像素电极，第二子像素电极，第一薄膜晶体管，第二薄膜晶体管和第三薄膜晶体管; 以及电荷调节控制线，其布置在所述第一基底上，所述电荷调节控制线和所述栅极线在所述第一子像素电极和所述第二子像素电极之间。 第一薄膜晶体管连接到栅极线，数据线和第一子像素电极; 第二薄膜晶体管连接到栅极线，数据线和第二子像素电极; 第三薄膜晶体管连接到电荷调节控制线，第一子像素电极和公共电极线。

公开(公告)号：US20160252793A1

公开(公告)日：2016-09-01

申请号：US14769405

申请日：2014-11-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Hongfei CHENG ,  Yong QIAO ,  Jianbo XIAN ,  Wenbo LI ,  Pan LI

IPC: G02F1/1362 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/1343 ,  G02F1/134309 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/1362 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2001/134372 ,  G02F2001/136218 ,  G02F2001/136295 ,  G02F2201/121 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/78669 ,  H01L29/7869

Abstract: The present disclosure provides an array substrate, a display panel, a display device and a method for manufacturing the array substrate. The array substrate includes: a plurality of gate lines and a plurality of data lines arranged in a crisscross manner on a base substrate, so as to define a plurality of subpixels; and a common electrode arranged opposite to each of the plurality of subpixels;. At least one of the subpixels is provided with a common electrode line connected to the common electrode at an identical subpixel region.

Abstract translation: 本发明提供一种阵列基板，显示面板，显示装置以及阵列基板的制造方法。 阵列基板包括：多个栅极线和在基底基板上以十字交叉的方式布置的多条数据线，以便限定多个子像素; 以及与所述多个子像素中的每一个相对配置的公共电极。 子像素中的至少一个在相同的子像素区域设置有与公共电极连接的公共电极线。

公开(公告)号：US20160246130A1

公开(公告)日：2016-08-25

申请号：US14785831

申请日：2015-06-01

Applicant: BOE Technology Group Co., Ltd.

Inventor： Wenbo LI ,  Xinyin WU ,  Pan LI ,  Hongfei CHENG ,  Jianbo XIAN

IPC: G02F1/1343 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/02 ,  H01L21/443 ,  H01L21/285 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  G02F1/1362 ,  H01L27/06

CPC classification number: G02F1/134309 ,  G02F1/13439 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/0447 ,  G09G2320/028 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/2855 ,  H01L21/443 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/518 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78669 ,  H01L29/7869

Abstract: The present application discloses an array substrate, a display panel and a display device. The array substrate comprises: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, each pixel unit comprising a first pixel electrode, a second pixel electrode, and at least three thin film transistors, the pixel unit further comprising: a charge-discharge element, the charge-discharge element and a third thin film transistor in the at least three thin film transistors charging and discharging the pixel unit such that the pixel unit forms a first voltage region and a second voltage region with different voltages.

Abstract translation: 本申请公开了阵列基板，显示面板和显示装置。 阵列基板包括：多条数据线和多条栅极线，由多条数据线和多条栅极线限定的多个像素单元，每个像素单元包括第一像素电极，第二像素电极， 以及至少三个薄膜晶体管，所述像素单元还包括：充电 - 放电元件，所述充电 - 放电元件和所述至少三个薄膜晶体管中的第三薄膜晶体管，对像素单元进行充电和放电，使得像素单元 形成具有不同电压的第一电压区域和第二电压区域。