Method and system of operating a bi-directional double-base bipolar junction transistor (B-TRAN)

    公开(公告)号:US11804835B2

    公开(公告)日:2023-10-31

    申请号:US17530981

    申请日:2021-11-19

    Inventor: Alireza Mojab

    CPC classification number: H03K17/668 H01L29/747

    Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: injecting charge carriers at a first rate into an upper base of the transistor, the injecting at the first rate results in current flow through the transistor from an upper collector-emitter to a lower collector-emitter, and the current flow results in first voltage drop measured across the upper collector-emitter and the lower collector-emitter; and then, within a predetermined period of time before the end of a first conduction period of the transistor, injecting charge carriers into the upper base at a second rate lower than the first rate, the injecting at the second rate results in second voltage drop measured across the upper collector-emitter and the lower collector-emitter, the second voltage drop higher than the first voltage drop; and then making the transistor non-conductive at the end of the conduction period.

    Method and system of operating a bi-directional double-base bipolar junction transistor (B-TRAN)

    公开(公告)号:US11522051B2

    公开(公告)日:2022-12-06

    申请号:US17537726

    申请日:2021-11-30

    Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET and thereby commutating a first shutoff current through a lower base of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

    RUGGEDIZED SYMMETRICALLY BIDIRECTIONAL BIPOLAR POWER TRANSISTOR

    公开(公告)号:US20210313461A1

    公开(公告)日:2021-10-07

    申请号:US17350254

    申请日:2021-06-17

    Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

    Ruggedized symmetrically bidirectional bipolar power transistor

    公开(公告)号:US11069797B2

    公开(公告)日:2021-07-20

    申请号:US15604822

    申请日:2017-05-25

    Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

    Power-Packet-Switching Circuits Using Stacked Bidirectional Switches

    公开(公告)号:US20190140548A1

    公开(公告)日:2019-05-09

    申请号:US16043945

    申请日:2018-07-24

    Abstract: Power-packet-switching circuits (and methods and systems) in which at least one port uses series-connected combinations of bidirectional switches to connect a link inductor (or transformer), with selectable polarity, to an outside line. Optionally, series-connected combinations of bidirectional switches are used for phase legs in some ports, while single bidirectional switches are used for the phase legs in other ports. This can be particularly advantageous where the converter interfaces between lines at significantly different operating voltages. By using B-TRANs as the series-combined elements of the combinations of switches, voltage-dividing circuitry is not needed to equalize the voltages seen by the individual devices in each combination.

    Power-Packet-Switching Circuits Using Stacked Bidirectional Switches

    公开(公告)号:US20170317575A1

    公开(公告)日:2017-11-02

    申请号:US15396362

    申请日:2016-12-30

    Abstract: Power-packet-switching circuits (and methods and systems) in which at least one port uses series-connected combinations of bidirectional switches to connect a link inductor (or transformer), with selectable polarity, to an outside line. Optionally, series-connected combinations of bidirectional switches are used for phase legs in some ports, while single bidirectional switches are used for the phase legs in other ports. This can be particularly advantageous where the converter interfaces between lines at significantly different operating voltages. By using B-TRANs as the series-combined elements of the combinations of switches, voltage-dividing circuitry is not needed to equalize the voltages seen by the individual devices in each combination.

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