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公开(公告)号：US09906222B2
公开(公告)日：2018-02-27
申请号：US15023380
申请日：2016-02-25
Inventor： Mang Zhao
IPC: G09G3/36 , H03K17/687
CPC classification number: H03K17/6872 , G09G3/3677 , G09G2310/0286
Abstract: A gate driving circuit and a liquid crystal display are disclosed. The gate driving circuit includes: an input and latch circuit, a signal processing circuit electrically connected with the input and latch circuit and an output buffering circuit electrically connected with the signal processing circuit. Wherein, the input and latch circuit or the signal processing circuit includes two switch modules which are disposed in parallel. Each switch module includes two switching tubes disposed in series, control terminals of the two switching tubes of one of the two switch modules are crosswise connected with control terminals of the two switching tubes of the other of the two switch modules. The present invention through disposing two switch modules and crosswise connecting the control terminals of the switching tubes, the stress degrees applied on the two switching transistors are the same so as to greatly increase the stability of the circuit operation.
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公开(公告)号：US09904135B1
公开(公告)日：2018-02-27
申请号：US15100299
申请日：2016-05-13
Inventor： Guangbao Fan
IPC: H01L29/786 , G02F1/1368 , G02F1/1362
CPC classification number: G02F1/1368 , G02F1/1362 , G02F1/136209 , G02F1/136227 , G02F2001/13685 , G02F2202/104 , H01L29/78621
Abstract: An array substrate and an LCD device are provided. The array substrate includes multiple LTPS thin-film transistors. Each transistor includes: a substrate; and a LTPS layer, a first insulation layer, a gate electrode, a second insulation layer, a source electrode, a drain electrode, a planarization layer, a first transparent conductive layer, a third insulation layer, a second transparent conductive layer and a connection metal layer. The LTPS layer, and gate electrode and the second insulation layer are sequentially disposed. The source electrode and the drain electrode are disposed on the second insulation layer, and connected with two terminals of the LTPS layer through the first and second through holes. The connection metal layer connects with the second transparent conductive layer and the drain electrode through a fourth through hole. The first transparent conductive layer is a common electrode and the second transparent conductive layer is a pixel electrode.
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公开(公告)号：US09904101B2
公开(公告)日：2018-02-27
申请号：US14655193
申请日：2015-04-07
Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. , WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Inventor： Chang Xie
IPC: G02F1/1335 , G02F1/1343 , G02F1/1368 , G02F1/137
CPC classification number: G02F1/133555 , G02F1/133526 , G02F1/133553 , G02F2001/133567
Abstract: A display panel and a display device module are disclosed. A TFT array substrate contained in the display panel includes a second substrate, a pixel electrode layer, a carrier layer, and a reflective layer. The second substrate includes a first region and a second region. A carrier platform contained in the carrier layer is disposed on the pixel electrode layer, in which a position of the carrier platform corresponds with the second region; and a reflection sheet contained in the reflective layer is disposed on the carrier platform, wherein the reflection sheet has a first reflective surface and a second reflective surface. The present invention improves the utilization of light in the backlight module.
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公开(公告)号：US20180053483A1
公开(公告)日：2018-02-22
申请号：US15802951
申请日：2017-11-03
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng XIAO , Mang ZHAO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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公开(公告)号：US20180053481A1
公开(公告)日：2018-02-22
申请号：US15802865
申请日：2017-11-03
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng XIAO , Mang ZHAO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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Patent Agency Ranking
公开(公告)号：US09898943B2
公开(公告)日：2018-02-20
申请号：US14906548
申请日：2015-12-30
Inventor： Xingling Guo , Jiehui Qin , Xiaoping Tan
IPC: G02F1/1345 , G09G3/00 , G09G3/36 , G02F1/13
CPC classification number: G09G3/006 , G02F1/1309 , G02F1/1345 , G02F1/13452 , G09G3/3648 , G09G2330/12 , H05K2201/10128
Abstract: The present disclosure provides a liquid crystal display module, which includes a liquid crystal display panel and a driver integrated circuit, wherein the liquid crystal display panel includes a testing pad, a first pad and a second pad, the first pad includes a first sub pad and a second sub pad which are separately disposed, the second sub pad is electrically connected to the testing pad, the driver integrated circuit includes at least two third pads, the third pads are respectively bonded to the first pad and the second pad; the first sub pad and the second sub pad are commonly bonded to one of the third pads, so as to achieve a short circuit between the first sub pad and the second sub pad. In the liquid crystal display module of the present disclosure, the space occupied by the bonding area is small.
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公开(公告)号：US09897881B2
公开(公告)日：2018-02-20
申请号：US14902551
申请日：2015-09-23
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Gui Chen , Caiqin Chen
IPC: H01L27/12 , G02F1/1368 , G02F1/1362 , G02F1/1343 , H01L29/786
CPC classification number: G02F1/1368 , G02F1/134309 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F1/136286 , G02F2001/13685 , G02F2201/121 , G02F2201/123 , G02F2201/40 , G02F2202/104 , H01L29/78633
Abstract: The present invention provides a thin film transistor array substrate and a liquid crystal display panel. The thin film transistor array substrate comprises: a substrate; a light shielding layer, located at a middle part on a surface of the substrate; a buffer layer, covering the light shielding layer; a Low Temperature Poly-silicon layer, being located on the buffer layer, and corresponding to the light shielding layer; an isolation layer, covering the Low Temperature Poly-silicon layer, and the isolation layer comprises a through hole, wherein a width of the through hole is smaller than a width of the light shielding layer; a metal layer, located on the isolation layer, and the metal layer is connected with the Low Temperature Poly-silicon layer via the through hole. The thin film transistor array substrate and the liquid crystal display panel have a higher aperture ratio.
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公开(公告)号：US09897737B2
公开(公告)日：2018-02-20
申请号：US14786049
申请日：2015-06-23
Inventor： Yan Cheng
CPC classification number: G02B6/0026 , G02B6/00 , G02B6/0023
Abstract: A quantum dot backlight module is disclosed. The quantum dot backlight module comprises a light source; a quantum dot layer, which emits fluorescence after being excited by light that is emitted by the light source; and a light guide plate, which guides the fluorescence that is emitted by the quantum dot layer to a needed direction, wherein the quantum dot layer is arranged on a light-entering side of the light guide plate, and a colloid layer is arranged between the light source and the quantum dot layer so as to enable the light source and the quantum dot layer to be bonded with each other closely, whereby the light source, the quantum dot layer, and the light guide plate are assembled together. According to the present disclosure, the light transmission mode of the light source after entering into the light guide plate is changed through changing the structure of the quantum dot backlight module, so that the light loss thereof can be reduced, and the light-emitting efficiency of the backlight module can be improved.
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629.发明申请公开(公告)号：US20180047830A1
公开(公告)日：2018-02-15
申请号：US14916187
申请日：2016-01-20
Inventor： Gaiping LU
IPC: H01L29/66 , H01L27/32 , H01L21/02 , H01L21/306 , H01L27/12 , H01L29/786
CPC classification number: H01L29/66757 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02667 , H01L21/30604 , H01L27/12 , H01L27/1229 , H01L27/1281 , H01L27/3272 , H01L29/786
Abstract: The disclosure relates to a low temperature polycrystalline silicon thin film transistor including: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer; a gate insulation layer formed on the buffer layer and the semiconductor layer; gates formed on the gate insulation layer; a dielectric layer formed on the gate insulation layer and the gates; a passivation layer formed on the dielectric layer; a first contact hole and a second contact hole formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and sources ad drains formed respectively on the first contact hole and the second contact hole; the semiconductor layer being a low temperature poly silicon layer, and a reflective layer and/or an insulation layer disposed between the buffer layer and the semiconductor layer. The disclosure further relates to a manufacturing method for aforementioned thin film transistor.
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公开(公告)号：US20180047764A1
公开(公告)日：2018-02-15
申请号：US15031279
申请日：2016-02-29
Inventor： Si Deng
IPC: H01L27/12 , H01L29/49 , G02F1/1343 , G02F1/1362 , G02F1/1333 , H01L29/786 , G02F1/1368
CPC classification number: H01L27/1288 , G02F1/133345 , G02F1/134309 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F1/1368 , G02F2001/133357 , G02F2001/134318 , G02F2001/134372 , G02F2001/136231 , G02F2001/13685 , G02F2202/104 , H01L21/77 , H01L27/02 , H01L27/1222 , H01L27/124 , H01L27/1251 , H01L27/1274 , H01L29/4908 , H01L29/78621 , H01L29/78633 , H01L29/78675
Abstract: The present invention provides an array substrate manufacturing method and an array substrate. The array substrate manufacturing method of the present invention uses an organic photoresist material to form a passivation protection layer (90) for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer (90) and a planarization layer (70) to exposure and development so as to obtain a third via (91) that is located above the first drain electrode (62) and a fourth via (92) that is located above the second drain electrode (64) and, thus, compared the prior art techniques, saves one mask and reduces one etching process so as to achieve the purposes of simplifying the manufacturing process and saving manufacturing cost. The array substrate of the present invention has a simple structure and low manufacturing cost and possesses excellent electrical performance.
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