公开(公告)号：US20180067351A1

公开(公告)日：2018-03-08

申请号：US15111822

申请日：2016-05-20

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Si Deng ,  Yuan Guo

IPC: G02F1/1362 ,  H01L21/77 ,  H01L21/02

CPC classification number: G02F1/1362 ,  G02F1/133516 ,  G02F1/136209 ,  G02F2001/136236 ,  G02F2001/136245 ,  G02F2001/13685 ,  G02F2201/40 ,  G02F2202/104 ,  H01L21/02595 ,  H01L21/02667 ,  H01L21/77 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/78621 ,  H01L29/78633

Abstract: The present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.

公开(公告)号：US20180373076A1

公开(公告)日：2018-12-27

申请号：US16129767

申请日：2018-09-12

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Si Deng ,  Yuan Guo

IPC: G02F1/1362 ,  H01L29/786 ,  H01L27/12 ,  H01L21/77 ,  H01L21/02 ,  G02F1/1368 ,  G02F1/1335

CPC classification number: G02F1/1362 ,  G02F1/133516 ,  G02F1/136209 ,  G02F2001/136236 ,  G02F2001/136245 ,  G02F2001/13685 ,  G02F2201/40 ,  G02F2202/104 ,  H01L21/02595 ,  H01L21/02667 ,  H01L21/77 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/78621 ,  H01L29/78633

Abstract: A manufacture method of a low temperature poly-silicon array substrate is provided. A halftone mask is utilized to realize a patterning process applied to a polysilicon layer and an N type heavy doping process of a polysilicon section of an NMOS region. In comparison with prior art, one mask is saved, and thus, the production cost is reduced, and a low temperature poly-silicon array substrate manufactured with such a process possesses excellent electronic property.

公开(公告)号：US10101620B2

公开(公告)日：2018-10-16

申请号：US15111822

申请日：2016-05-20

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Si Deng ,  Yuan Guo

IPC: H01L21/00 ,  G02F1/1362 ,  H01L21/02 ,  H01L21/77 ,  G02F1/1335 ,  H01L29/786 ,  G02F1/1368

Abstract: The present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.

公开(公告)号：US10473990B2

公开(公告)日：2019-11-12

申请号：US16129767

申请日：2018-09-12

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Si Deng ,  Yuan Guo

IPC: H01L21/00 ,  G02F1/1362 ,  H01L21/77 ,  H01L21/02 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1335 ,  G02F1/1368

Abstract: A manufacture method of a low temperature poly-silicon array substrate is provided. A halftone mask is utilized to realize a patterning process applied to a polysilicon layer and an N type heavy doping process of a polysilicon section of an NMOS region. In comparison with prior art, one mask is saved, and thus, the production cost is reduced, and a low temperature poly-silicon array substrate manufactured with such a process possesses excellent electronic property.

公开(公告)号：US20180366498A1

公开(公告)日：2018-12-20

申请号：US16101534

申请日：2018-08-13

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Si Deng

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1333 ,  H01L29/49 ,  H01L27/02 ,  H01L21/77 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

Abstract: An array substrate manufacturing method and an array substrate are provided. The array substrate manufacturing method uses an organic photoresist material to form a passivation protection layer for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer and a planarization layer to exposure and development so as to obtain a third via that is located above the first drain electrode and a fourth via that is located above the second drain electrode and, thus, compared to the prior art techniques, saves one mask and reduces one etching process so as to achieve the purposes of simplifying the manufacturing process and saving manufacturing cost. The array substrate so manufactured has a simple structure and a low manufacturing cost and possesses excellent electrical performance.

公开(公告)号：US10068933B2

公开(公告)日：2018-09-04

申请号：US15031279

申请日：2016-02-29

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Si Deng

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1343

Abstract: The present invention provides an array substrate manufacturing method and an array substrate. The array substrate manufacturing method of the present invention uses an organic photoresist material to form a passivation protection layer (90) for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer (90) and a planarization layer (70) to exposure and development so as to obtain a third via (91) that is located above the first drain electrode (62) and a fourth via (92) that is located above the second drain electrode (64) and, thus, compared the prior art techniques, saves one mask and reduces one etching process so as to achieve the purposes of simplifying the manufacturing process and saving manufacturing cost. The array substrate of the present invention has a simple structure and low manufacturing cost and possesses excellent electrical performance.

公开(公告)号：US20180047764A1

公开(公告)日：2018-02-15

申请号：US15031279

申请日：2016-02-29

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Si Deng

IPC: H01L27/12 ,  H01L29/49 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1333 ,  H01L29/786 ,  G02F1/1368

CPC classification number: H01L27/1288 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/133357 ,  G02F2001/134318 ,  G02F2001/134372 ,  G02F2001/136231 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L21/77 ,  H01L27/02 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1274 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78675

Abstract: The present invention provides an array substrate manufacturing method and an array substrate. The array substrate manufacturing method of the present invention uses an organic photoresist material to form a passivation protection layer (90) for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer (90) and a planarization layer (70) to exposure and development so as to obtain a third via (91) that is located above the first drain electrode (62) and a fourth via (92) that is located above the second drain electrode (64) and, thus, compared the prior art techniques, saves one mask and reduces one etching process so as to achieve the purposes of simplifying the manufacturing process and saving manufacturing cost. The array substrate of the present invention has a simple structure and low manufacturing cost and possesses excellent electrical performance.