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公开(公告)号：US09805730B2
公开(公告)日：2017-10-31
申请号：US14458389
申请日：2014-08-13
Applicant: iZettle Merchant Services AB
Inventor： Fredrik Munter
Abstract: The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises pre-processing the received encoded data signal; scanning the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating an actual frequency based on the detected start sequence; interpreting, a data block succeeding the start sequence using the assessed actual frequency; and assessing whether to request adjustment of the adjustable encoder clock frequency based on the scanning and/or the interpretation. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program.
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公开(公告)号：US09793879B2
公开(公告)日：2017-10-17
申请号：US14857681
申请日：2015-09-17
Applicant: Avnera Corporation
Inventor： Xudong Zhao
IPC: G10L21/00 , G10L19/00 , H03M13/33 , H03M13/00 , H03M13/27 , H03H17/06 , G10L21/0316 , H03M7/00 , H03M5/00 , G10L21/0356 , H03H17/02 , G10L19/24
CPC classification number: H03H17/0628 , G10L19/00 , G10L19/24 , G10L21/0316 , G10L21/0356 , G10L2019/001 , H03H17/028 , H03M5/00 , H03M7/00 , H03M13/00 , H03M13/27 , H03M13/33
Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.
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公开(公告)号：US20170264906A1
公开(公告)日：2017-09-14
申请号：US15214353
申请日：2016-07-19
Inventor： Lei DAI , Taehyun KIM
Abstract: The present disclosure relates to an encoder and an encoding method thereof, as well as a decoder and a decoding method thereof, which can be used to reduce the number of wires necessary for data transmission and transmit more data at a faster speed with the same number of wires, thereby improving the efficiency of data transmission. The encoder may comprises two input terminals configured to receive two input signals simultaneously, each input terminal comprises a wire identifying a positive voltage and a wire identifying a negative voltage; and a plurality of output terminals, wherein each output terminal comprises a wire identifying a positive voltage and a wire identifying a negative voltage, a combination of the two input signals corresponds to one of the plurality of output terminals, and the output terminal to which the current combination of the two input signals corresponds is configured to output signals through the two wires of the output terminal.
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公开(公告)号：US09667271B2
公开(公告)日：2017-05-30
申请号：US15358909
申请日：2016-11-22
Applicant: International Business Machines Corporation
Inventor： Frederic J. Bauchot , Marc Joel Herve Legroux
CPC classification number: H03M7/3084 , G06F12/0207 , H03M5/00 , H03M5/14 , H03M7/00 , H03M7/30 , H03M7/40 , H03M7/4025 , H03M9/00 , Y02D10/13
Abstract: This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.
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公开(公告)号：US20170117820A1
公开(公告)日：2017-04-27
申请号：US15397909
申请日：2017-01-04
Applicant: Mitsubishi Electric Corporation
Inventor： Akiko GOTO
CPC classification number: H02M7/487 , H01L29/00 , H02M1/088 , H02M2001/0009 , H02M2001/0054 , H03K17/107 , H03K17/6874 , H03K17/74 , H03M5/00 , H03M7/00
Abstract: First and second external terminals are connected to high-voltage and low-voltage terminals, respectively, of a direct-current voltage source circuit in which first and second direct-current voltage sources are connected in series. A third external terminal is connected to a connecting point between the first and second direct-current voltage sources. A first switching element is connected between the first and fourth external terminals. A second switching element is connected between the fourth and second external terminals. A first AC switch unit includes third and fourth switching elements connected in inverse series between the third and fourth external terminals. A second AC switch unit includes fifth and sixth switching elements connected in inverse series between the third and fourth external terminals. The first and second AC switch units are connected in parallel. The first and second switching elements and the first and second AC switch units are incorporated in one module.
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Patent Agency Ranking
公开(公告)号：US20160294412A1
公开(公告)日：2016-10-06
申请号：US15184306
申请日：2016-06-16
Applicant: International Business Machines Corporation
Inventor： Frederic J. Bauchot , Marc Joel Herve Legroux
CPC classification number: H03M7/3084 , G06F12/0207 , H03M5/00 , H03M5/14 , H03M7/00 , H03M7/30 , H03M7/40 , H03M7/4025 , H03M9/00 , Y02D10/13
Abstract: This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.
Abstract translation: 本发明涉及一种用于编码二进制字符输入串的系统，方法和计算机程序产品，包括：包括起始空单元的蜂窝数据结构定义; 定义通过数据结构的路径的一个或多个路径定义; 用于将具有预定义的初始位置的二进制字符写入空单元的字符读写引擎; 下一个小区确定引擎，用于通过以数据结构中的一个路径方式地检查小区来确定下一个空单元，直到找到一个空单元; 循环辅助器，用于循环回到写入下一个字符步骤，并确定下一个单元步骤，直到没有更多的数据字符或下一个空单元格未被确定; 以及用于将数据结构有序地串行化为表示字母数字字符的编码字符串的一维二进制字符串的序列化反序列化引擎。
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公开(公告)号：US09425825B2
公开(公告)日：2016-08-23
申请号：US14947101
申请日：2015-11-20
Applicant: International Business Machines Corporation
Inventor： Frederic J. Bauchot , Marc Joel Herve Legroux
CPC classification number: H03M9/00 , G06F17/2217 , H03M5/00 , H03M7/14 , H03M7/30 , H03M7/40 , H03M7/4025
Abstract: This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.
Abstract translation: 本发明涉及用于编码二进制字符的输入串的系统，方法和计算机程序产品，包括：包括起始空单元的蜂窝数据结构定义; 定义通过数据结构的路径的一个或多个路径定义; 用于将具有预定义的初始位置的二进制字符写入空单元的字符读写引擎; 下一个小区确定引擎，用于通过以数据结构中的一个路径方式地检查小区来确定下一个空单元，直到找到一个空单元; 循环辅助器，用于循环回到写入下一个字符步骤，并确定下一个单元步骤，直到没有更多的数据字符或下一个空单元格未被确定; 以及用于将数据结构有序地串行化为表示字母数字字符的编码字符串的一维二进制字符串的序列化反序列化引擎。
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58.发明申请DECODING DEVICE, INFORMATION TRANSMISSION SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM 有权解码设备，信息传输系统和非终端计算机可读介质公开(公告)号：US20160191205A1
公开(公告)日：2016-06-30
申请号：US14689850
申请日：2015-04-17
Applicant: FUJI XEROX CO., LTD.
Inventor： Tsutomu HAMADA , Yoshinori AWATA , Atsushi UGAJIN
CPC classification number: H04L1/0045 , H03M5/00 , H03M5/14 , H03M13/19 , H04L1/0042 , H04L1/0063
Abstract: Provided is a decoding device including a reception unit that receives data of which the number of bits is converted and encoded such that a ratio between appearance frequency of a first code and appearance frequency of a second code is a predetermined range, and to which an error correcting code including redundant bits for calculating an error position of the data and a parity check bit of the data is appended, and a detection unit that detects that there are an odd number of bit errors in the data when a value of a syndrome corresponding to an error position is a first predetermined value and an error occurs in the decoding, or when the value of the syndrome is not the first value and a value of the parity check bit is a second predetermined value and an error occurs in the decoding on the data.
Abstract translation: 提供了一种解码装置，包括：接收单元，接收对数据进行转换和编码的数据，使得第一代码的出现频率与第二代码的出现频率之间的比率是预定范围，并且错误 附加了包括用于计算数据的错误位置的冗余位和数据的奇偶校验位的校正码，以及检测单元，当检测到对应于所述数据的综合征的值时，检测到数据中存在奇数个位错误 误差位置是第一预定值，并且在解码中出现错误，或者当校正子的值不是第一值并且奇偶校验位的值是第二预定值，并且在解码时出现错误 数据。
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公开(公告)号：US20160149729A1
公开(公告)日：2016-05-26
申请号：US14949290
申请日：2015-11-23
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku
CPC classification number: G06F11/1004 , H03M5/00 , H03M13/03 , H03M13/63 , H04L1/004 , H04L1/0041 , H04L1/0061 , H04L1/245 , H04L7/033 , H04L25/0264 , H04L25/0272 , H04L25/03286 , H04L25/14 , H04L25/493 , H04L27/38
Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.
Abstract translation: 公开了用于在多线接口上的传输中的错误检测的装置，系统和方法。 用于校正多线转换编码接口中的传输错误的方法可以包括基于接收到的多个比特中的错误检测码（EDC）的值来确定符号序列中是否存在符号错误，生成一个或 符号序列的更多排列，其中每个置换包括不同于符号序列中的对应符号并且不同于其他排列中的对应符号的一个符号。 一个或多个排列中的排列可以被识别为当其产生与期望的EDC值匹配的解码的EDC值时包括经校正的符号序列。 期望的EDC值可以对应于通过多线接口发送的EDC的预定义值，以使得能够在接收器处检测多达两个符号错误。
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公开(公告)号：US20160147596A1
公开(公告)日：2016-05-26
申请号：US14949435
申请日：2015-11-23
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku
CPC classification number: G06F11/1004 , H03M5/00 , H03M13/03 , H03M13/63 , H04L1/004 , H04L1/0041 , H04L1/0061 , H04L1/245 , H04L7/033 , H04L25/0264 , H04L25/0272 , H04L25/03286 , H04L25/14 , H04L25/493 , H04L27/38
Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.
Abstract translation: 公开了用于在多线接口上的传输中的错误检测的装置，系统和方法。 一种用于在多线接口上发送数据的方法，包括：在多线接口上发送数据包括获得要在多个连接器上发送的多个比特，将所述多个比特转换成符号序列，以及发送所述序列 的多个连接器上的符号。 多个位中的预定数量的最低有效位可用于错误检测。 预定数量的最低有效位可以具有不同于多个误差值中的每一个的常数值。 影响符号序列中的一个或两个符号的符号错误可能导致预定数量的最低有效位的解码版本具有作为多个误差值之一的值。
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